10M/100M/1G/10G/25G Unmanaged Ethernet Switch

Overview

Silicon-Agnostic, Compact and Highly flexible Ethernet Switch IPs

Unmanaged Ethernet Switch IP cores are a family of Ethernet switching IPs that provide a variety of port configurations, including 1G, 1G/10G, 10G, and 10G/25G options. The unmanaged Ethernet switch IP cores family is a size-optimized implementation of non-blocking crossbar switches designed to support wire-speed packet processing and forwarding.

The unmanaged Ethernet switch IP cores family features FCS validation/recalculation, MAC learning/forwarding/ageing and VLAN tagging including implementing a store-and-forward switching architecture.

The number of ports is configurable at compile time, making the unmanaged Ethernet switch IP cores solution highly flexible and the solutions from Comcores are silicon-agnostic, making them suitable for implementation in any ASIC, FPGA, or ASSP technology.

Key Features

Delivers Performance

  • Automatic MAC address learning and aging
  • Support programmable static forwarding entries
  • Ethernet Multicast support
  • Full duplex Ethernet interfaces
  • Supports Access port VLAN and Trunk port VLAN operation

Highly Configurable

  • Configurable for up to 16 + 4 ports at compile time
  • Supports configurable queuing behaviour, including round-robin and fair queuing

Easy to Use

  • Compatible with GMII, RGMII, XGMII, and XXVMII interfaces for seamless connection to external Physical Layer devices (PHYs)
  • Easy integration with standard Xilinx AXI4 Lite control interface
  • Can be implemented with or without an external microcontroller

Silicon Agnostic

  • Designed in Verilog and targeting both ASICs and FPGAs

Block Diagram

10M/100M/1G/10G/25G Unmanaged Ethernet Switch Block Diagram

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual and Release Note
  • Simulation Environment, including Simple Testbed, Test case and Test Script
  • Programming Register Specification
  • Timing Constraints in Synopsys SDC format
  • Access to support system and direct support from Comcores Engineers
  • Synopsys SGDC Files (optional)
  • Synopsys Lint, CDC and Waivers (optional)

Technical Specifications

Short description
10M/100M/1G/10G/25G Unmanaged Ethernet Switch
Vendor
Vendor Name
Maturity
Mature
Availability
Available
×
Semiconductor IP