The 1G and 10G Switching Ethernet Subsystem dynamically switches an Ethernet Media Access Controller (MAC) between 1G or 10G physical coding sublayer/physical layer (PCS/PHY). The IP core is delivered as encrypted register transfer level (RTL) through the Vivado® Design Suite.
Targeted for Xilinx UltraScale+ devices. The Subsystem is included with the 10G/25G Ethernet MAC/PCS Subsystem.
1G/10G/25G Switching Ethernet Subsystem
Overview
Key Features
- Supports 1.25G or 10.3125G Ethernet
- Both media access control (MAC) and physical coding sublayer/physical medium attachment (PCS/PMA) functions are included
- Detailed statistics gathering
- Optional support for IEEE 1588 2-step hardware timestamping
Technical Specifications
Related IPs
- 200G/400G Ethernet Subsystem
- 1G/10G/25G/50G/100G Ethernet Switch IP Core - Efficient and Massively Customizable
- DO-254 Tri-Mode Ethernet Media Access Controller (TEMAC) 1.00a
- Switching regulator to supply digital islet
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- Switching regulator, inductor-based, in dual mode (PFM and PWM), high efficiency