General Purpose DSP IP
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Ultra-low-power Processor based on RISC-V Architecture
- The icyflex-V processor is a new ultra-low-power core based on the RISC-V 32-bit ISA, compatible with off-the-shelf open-source and/or proprietary programming tools.
- This new development represents a cost effective yet performing alternative to proprietary cores for next-generation ultra-low-power system-on-chip developments.
- The core was optimized for performance, code density and power consumption and delivers up to 3.2 CoreMark/MHz while consuming as low as 14 uA/MHz in TSMC 55 nm low-power process.
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18-Bit Pipeline DSP Slice IP
- Timing resolution: 80ps
- Operating frequency range: 160MHz – 700 MHz
- Lock time: 11 cycles
- Generates user configurable precise phase shifts from 00 to 3600 with a resolution of 10
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Ultra low power C-programmable Baseband Signal Processor core
- Ultra low power consumption
- Highly optimizing C-compiler software toolkit
- Minimal core size (65k gates), excluding debug interface (6k gates)
- Small memory footprint
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Ultra low power C-programmable DSP core
- Ultra low power consumption
- Highly optimizing C-compiler software toolkit
- Minimal core size (43k gates), excluding debug interface (6k gates)
- Small memory footprint
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Tensilica FloatingPoint KQ7/KQ8 DSPs
- VLIW parallelism issuing multiple concurrent operations per cycle
- 512-bit and 1024-bit SIMD
- IEEE 754 vector floating-point (HP, SP, DP)
- Performance-optimized fused multiply-add (FMA)
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Tensilica FloatingPoint KP1/KP6 DSPs
- VLIW parallelism issuing multiple concurrent operations per cycle
- Xtensa LX Secure Mode
- 128-bit and 512-bit SIMD
- IEEE 754 vector floating-point
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Single precision floating-point fast speed parametrized multi operands adder
- Synthesizable, technology independent Verilog HDL Core.
- 32 bits floating-point arithmetic.
- IEEE 754 compliant. ● High-speed fully pipelined architecture.
- Only 7 clock-cycles of latency.