ESD Protection IP
ESD (Electrostatic Discharge) Protection IP cores provide efficient defense against electrostatic discharges, reducing the risk of failure and enhancing product performance. By incorporating ESD protection into your designs, you can meet industry standards, improve device robustness, and ensure your products remain durable in real-world environments.
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ESD Protection IP
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ESD Protection IP
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ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
- A Wirebond and FlipChip compatible <80fF ESD Solutions for Multi-Gigabit SerDes Applications.
- This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor applications.
- Featuring low-capacitance LVDS differential pairs (<250fF per pin) at 0.8V, this library ensures superior signal integrity for high-speed applications.
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High-Speed 3.3V I/O library with 8kV ESD Protection in TSPCo 65nm
- A 3.3V wirebond I/O library with 8kV HBM ESD protection, a 1.2Gbps LVDS, GPIO, and I2C compliant ODIO in an ultra-small footprint.
- This library ensures robust reliability in challenging environments, with capabilities including 8kV HBM, 500V CDM, and a robust 2kV IEC 61000-4-2 system stress capability.
- Its compact footprint makes it ideal for applications where size is critical.
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Power and Ground BondPads that include CC-100IP Digital and Switching Circuit Power Reduction Technology, Featuring 20% to 40% Total Dynamic Power Reduction
- 20% to 40% Digital and Dynamic Power Reduction
- Fits into any IC bondpad
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A 28nm 1.8V-3.3V Fail-Safe General-Purpose IO & OSC
- Fail-Safe GPIO in TSMC 28nm process technology
- Physical features
- This library also features a 33MHz OSC (3.3V).
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LVDS IO Pad Set
- Powered from 1.8V ±10% and 1.0V (±10%) to 1.1V (-10%/+5%) core power supplies
- Operates up to 1.2GHz (2.4Gbps)
- Input receive sensitivity of 75mV peak differential (without hysteresis)
- Common mode range from 0V to 2.4V (limited by Power Supply)
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5V I/O and ESD in TSMC 12nm FFC/FFC+
- A 5V Library for Generic I/O and ESD Applications TSMC 12NM FFC/FFC+ process.
- This library is a base set of ESD protection structures for I/O and Power supplies. The design targets up to 8A applications (>8kV HBM).
- The I/Os are designed to trigger and protect interfaces during Electrical Overstress (EOS) events during normal operation.
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RF ESD library in TSMC 55nm LP
- RF ESD cells in TSMC 55nm LP targetting low-capacitance ESD protection.
- This library is a production-quality, silicon-proven ESD library in TSMC 55nm.
- The library does not have general ESD architecture as it is not a full I/O, but rather is a collection of standalone ESD cells that target low-capacitance RF ESD protection.