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DRAM IP
from 2 vendors
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4)
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LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
- Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
- x16 and x32 channel support
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LPDDR5X/5/4X/4 combo PHY at 7nm
- Unbeatable performance-driven and low-power-driven PPA
- Ultra-low read/write latency with programmable PHY boundary timing
- Channel equalization with FFE and DFE
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DDR5 Registering Clock Driver (RCD) (DDR5RCD01)
- Compliance as per JEDEC's JESD82-511
- In I3C mode, SCL Operating speed 12.5MHz as Maximum
- DDR5 server speeds up to 4800MT/s
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DDR5 Registering Clock Driver (RCD) (DDR5RCD03)
- Compliance as per JEDEC's JESD82-513
- In I3C mode, SCL Operating speed 12.5MHz as Maximum
- DDR5 server speeds up to 6000MT/s