FIFO/LIFO IP

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Compare 12 FIFO/LIFO IP from 4 vendors (1 - 10)

Searchable Synchronous FIFO
- The FIFO-CAM controls are designed to operate over a wide range of clock frequencies.
- The interface signals are fully synchronous; no asynchronous signals are present on either side.
- Only reset may be asynchronous in that it may be asserted asynchronously and synchronized internally to the clock.
Asynchronous FIFO with configurable flags and counts
- The aFIFO2 controls are designed to ensure hazard free clock domain crossing between the read and write ports.
- Only single control lines are re-synchronized between the two clock domains ensuring hazard free operation.
- The requirement for Gray coded addressing is thus eliminated. A wide range of clock frequencies and relative frequencies between read and write ports are fully tolerated.
Synchronous FIFO with second read/write port as companion to A2_CAM_FIFO
- Synchronous FIFO with second read/write port as companion to A2_CAM_FIFO
FIFO capable of working in Highly Noisy environment, giving silicon ultimate stability in electromagnetic noisy environment.
- Key Design Feature -
- 1. Synthesizable, Technology Independent, Verilog IP Core.
- 2. Configurable Data Width and FIFO Depth.
- 3. Noise resistant Dual Asynchronous Clock Architecture.
DO-254 FIFO Generator 1.00a
- FIFO depths up to 4,194,304 words
- FIFO data widths from 1 to 1024 bits for Native FIFO configurations and up to 4096 bits for AXI FIFO configurations
- Non-symmetric aspect ratios (read-to-write port ratios ranging from 1:8 to 8:1)
- Supports Independent or common clock domains
This fifo access external OnChip dual port memory to store data.
- 1. Configurable Depth.
- 2. Configurable Width.
- 3. Configurable Clock freq.
- 4. External Dual Port Memory for Storage
This is a Generic fifo with configurable Depth, Configurable Width and Different Clock Domain Crossing options.
- 1. Configurable Depth.
- 2. Configurable Width.
- 3. Configurable Clock freq.
This fifo uses external onchip single port memory to store data.
- 1. Configurable Depth.
- 2. Configurable Width.
- 3. Configurable Clock freq.
- 4. Uses External OnChip Single Port Memory for Storage of Data
This is a Collection of different kind of FIFOs and Elastic buffers.
- Features -
- This is a Generic fifo with configurable Depth, Configurable Width and Clock Domain Crossing options.
- Fully Stable, CDC Proven, Non2**n depth supported FIFOs.
This is capable to transferring data even when internal or exteral clock swings and overlaps each other
- 1. Configurable Depth.
- 2. Configurable Width.
- 3. Configurable Clock freq.
- 4. Configurable Data Release Duration.