FIFO/LIFO IP
Welcome to the ultimate FIFO/LIFO IP hub! Explore our vast directory of FIFO/LIFO IP
All offers in
FIFO/LIFO IP
Filter
Compare
13
FIFO/LIFO IP
from 4 vendors
(1
-
10)
-
FIFO capable of working in Highly Noisy environment, giving silicon ultimate stability in electromagnetic noisy environment.
- Key Design Feature -
- 1. Synthesizable, Technology Independent, Verilog IP Core.
- 2. Configurable Data Width and FIFO Depth.
- 3. Noise resistant Dual Asynchronous Clock Architecture.
-
This is a Collection of different kind of FIFOs and Elastic buffers.
- Features -
- This is a Generic fifo with configurable Depth, Configurable Width and Clock Domain Crossing options.
- Fully Stable, CDC Proven, Non2**n depth supported FIFOs.
-
This is capable to transferring data even when internal or exteral clock swings and overlaps each other
- 1. Configurable Depth.
- 2. Configurable Width.
- 3. Configurable Clock freq.
- 4. Configurable Data Release Duration.
-
This fifo uses external onchip single port memory to store data.
- 1. Configurable Depth.
- 2. Configurable Width.
- 3. Configurable Clock freq.
- 4. Uses External OnChip Single Port Memory for Storage of Data
-
This fifo access external OnChip dual port memory to store data.
- 1. Configurable Depth.
- 2. Configurable Width.
- 3. Configurable Clock freq.
- 4. External Dual Port Memory for Storage
-
This is a Generic fifo with configurable Depth, Configurable Width and Different Clock Domain Crossing options.
- 1. Configurable Depth.
- 2. Configurable Width.
- 3. Configurable Clock freq.
-
FIFO Generator
- FIFO depths up to 4,194,304 words
- FIFO data widths from 1 to 1024 bits for Native FIFO configurations and up to 4096 bits for AXI FIFO configurations
- Non-symmetric aspect ratios (read-to-write port ratios ranging from 1:8 to 8:1)
- Supports Independent or common clock domains
-
DO-254 FIFO Generator 1.00a
- FIFO depths up to 4,194,304 words
- FIFO data widths from 1 to 1024 bits for Native FIFO configurations and up to 4096 bits for AXI FIFO configurations
- Non-symmetric aspect ratios (read-to-write port ratios ranging from 1:8 to 8:1)
- Supports Independent or common clock domains
-
Asynchronous FIFO alternate design
- Configurable for width and depth
- Configurable for fallthrough
-
Asynchronous FIFO with flags and depth counter
- Configurable for width and depth
- Configurable for fallthrough