LPDDR5 IP

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Compare 103 LPDDR5 IP from 15 vendors (1 - 10)
  • LPDDR5X/5/4X/4 PHY & Controller
    • The DDR IP Mixed-Signal LPDDR5X/5/4X/4 Combo PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices
    • It is optimized for low-power and high-speed applications with robust timing and small silicon area
    • It supports all JEDEC LPDDR5X/5/4X/4 SDRAM components in the market
    • The PHY components contain DDR-specialized functional and utility high-performance I/Os, critical timing synchronization modules (TSM), and low power/jitter DLLs with programmable fine-grain control for any SDRAM interface
    Block Diagram -- LPDDR5X/5/4X/4 PHY & Controller
  • LPDDR5X/5/4X/4 combo PHY at 12nm
    • Compliant with JEDEC JESD209-5C for LPDDR5x/5/4x/4 with PHY standards
    • Delivering up to 8533Mbps
    • DFI 5.1 specification PHY Interface Compliant
    • Support up to 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR5X/5/4X/4 combo PHY at 12nm
  • LPDDR5X/5/4X/4 PHY for 16nm
    • Compliant with JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
    • DFI 5.0 Interface Compliant
    • Supports up to 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR5X/5/4X/4 PHY for 16nm
  • LPDDR5/4x/4 combo PHY on 14nm, 12nm
    • Compliant with JEDEC standards for LPDDR5/4x/4 with PHY standards
    • DFI 5.0 Interface Compliant
    • Supports 1,2, or 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR5/4x/4 combo PHY on 14nm, 12nm
  • LPDDR5/4x/4 PHY IP for Samsung 14LPU
    • Compliant with JEDEC standards for LPDDR5/4x/4 with PHY standards
    • DFI 5.0 Interface Compliant
    • Supports 1,2, or 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR5/4x/4 PHY IP for Samsung 14LPU
  • Memory Controller
    • JEDEC GDDR6 standard JESD250B
    • Fast frequency switching
    • Flexible Configuration
    Block Diagram -- Memory Controller
  • LPDDR5T / LPDDR5X / LPDDR5 Controller
    • Support for all LPDDR5T/5X/5 devices
    • Bank management logic monitors status of each bank
    • Queue-based user interface with reordering scheduler
    • Look-ahead activate, precharge, and auto-precharge logic
    • Parity protection for all stored control registers
    • PHY interface based on DFI 5.1 standard
    Block Diagram -- LPDDR5T / LPDDR5X / LPDDR5 Controller
  • LPDDR5 Controller - Validates memory controllers for high-speed, power-efficient performance
    • LPDDR5 Verification IP (VIP) is a tool designed to simulate and validate the functionality of LPDDR5 memory controllers. It ensures compliance with LPDDR5 specifications, covering high-speed data transfer, power management, error detection, and system integration.
    • LPDDR5 VIP is essential across various industries, enabling high-performance systems to function optimally. It is utilized in mobile devices, automotive systems, high-performance computing, AI/ML, and more, ensuring efficient memory interfaces in diverse applications
    Block Diagram -- LPDDR5 Controller - Validates memory controllers for high-speed, power-efficient performance
  • LPDDR4/4x/5/5x PHY
    • Supports JEDEC SDRAM standards including LPDDR4 (1.1V), LPDDR4x (0.6V), LPDDR5/5x (0.5V)
    • Supports data rates up to 4,266 Mbps LPDDR4/LPDDR5 and up to 8,533 Mbps LPDDR5x
    • Support for 16, 32 and 64-bit operation
    Block Diagram -- LPDDR4/4x/5/5x PHY
  • LPDDR5 IP solution
    • Support LPDDR5 up to 6400Mbps
    • Support Channel equalization with 1-tap DFE
    • Support single-ended mode on CK, WCK and read DQS below 3200Mbps
    • Support Link ECC for RDQS and DM
    Block Diagram -- LPDDR5 IP solution
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