DisplayPort IP

Silicon proven on multiple ASIC and FPGA processes
Capable of operating without a host CPU in low complexity applications
Horizontal and vertical video delimiter signals with 1, 2 or 4 pixels per output cycle, supporting up to 16K resolution output; deep color and HDR support
1.62 to 8.1 Gbps link rate across 1, 2, or 4 lanes

Our 6th generation DisplayPort Transmitter Link Controller core supports DisplayPort 2.1, DisplayPort 1.4a and embedded DisplayPort 1.5.
Features include link rates up to 20Gbps for DisplayPort 2.0, 8.1Gbps for DisplayPort 1.4a. Display Steam Compression (DSC), multi-stream transport (MST) and more. The base core includes all required link functionality— Main Link, Secondary Channel, and AUX Channel protocols—and supports the HDCP 2.3 standards for data encryption.

The DisplayPort Multi Stream Transport (MST) Topology Management Software implements MST topology management for multiple monitors on a Trilinear DisplayPort Transmitter IP core.
The software enables customers to shorten time to market and reduce design risk using pre-tested, ready-to-deploy software.

The DisplayPort Link Policy Maker (LPM) is a DisplayPort 1.4/2.0 compliant software stack that manages and controls the DisplayPort serial link and AUX channel communications.
The software provides for enumeration and configuration of the source and sink devices, adaptive training of the DisplayPort link, video stream allocation and transmission, AUX channel traffic management and handling of all HPD (Hot Plug Detect) events.

Intel now offers a fully VESA-compliant DisplayPort Intel® FPGA IP core v1.4
The DisplayPort IP core is found prevalently in many video-related products servicing a wide variety of applications and has the following features:

The DP/eDP IP is designed for transmitting or receiving video and audio signals between the video source devices and display devices
It is fully compliant with DP1.4 and eDP1.4 specifications
The IP provides both PHY and controller solutions, offering a reliable implementation for DisplayPort and embedded DisplayPort interfaces that can be seamlessly integrated in the SoCs used in multimedia devices

VESA DisplayPort 1.4 compliant
Reed-Solomon RS (254,250) FEC, 10-bit symbols
Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
DisplayPort main 8b/10b encoder included (Tx only)
Status and control can be done with signals or optionally via an integrated APB register module (Rx)

VESA DisplayPort 1.4 compliant
Reed-Solomon RS (254,250) FEC, 10-bit symbols
Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
DisplayPort main 8b/10b encoder included (Tx only)
Status and control can be done with signals or optionally via an integrated APB register module (Rx)

DisplayPort is a high-performance digital display interface designed for connecting computers, monitors, and other video devices. It supports high-definition and ultra-high-definition displays, offering top-tier video and audio transmission.
In Verification IP (VIP), DisplayPort ensures the accurate functioning of display controllers, validating the transmission of video and audio data. VIP verifies compliance with DisplayPort standards, ensuring seamless integration with a wide range of devices.