IP Catalog > Interface IP Cores > MIPI IP > MIPI Controller IP > MIPI SoundWire IP

MIPI SoundWire IP

MIPI SoundWire IP is a high-performance interface designed to enable efficient, low-latency audio communication between processors and audio peripherals in mobile and embedded devices. As part of the MIPI (Mobile Industry Processor Interface) standard, MIPI SoundWire IP supports high-quality, multi-channel audio transmission, making it ideal for applications such as smartphones, wearables, automotive infotainment systems, and smart home devices.

All offers in MIPI SoundWire IP
Filter
Filter

Login required.

Sign in

Search (15)
Compare 15 MIPI SoundWire IP from 5 vendors (1 - 10)
  • MIPI SWI3S Manager Core IP
    • The SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer the Audio streams and the Control information together.
    • One or more SWI3S Peripheral IP can be connected specific to the application.
    Block Diagram -- MIPI SWI3S Manager Core IP
  • MIPI SoundWire Slave Controller 1.2
    • MIPI SoundWire®Slave Controller, typically integrated into audio DSP/Codecs or directly into audio peripherals such as Microphones and Amplifiers used in smart phones, tablets and mobile PCs. 
    • The IP when integrated provides SoundWire, a new audio interface to connect to Master typically embedded in Application Processor or Audio Codecs.
    Block Diagram -- MIPI SoundWire Slave Controller 1.2
  • MIPI SoundWire Master Controller 1.2
    • Compliant with MIPI SoundWire specification version 1.2
    • Configurable number of Data Ports Configurable Direction – Source or Sink
    • Implements clock gearbox with programmable frequency divider
    • Implements SoundWire Bus Clock Stop and WakeUp detection
    Block Diagram -- MIPI SoundWire Master Controller 1.2
  • Simulation VIP for MIPI SoundWire-I3S
    • PHYs
    • Supports LC PHY and DLV PHY
    • Interfaces
    • Supports serial interface
    Block Diagram -- Simulation VIP for MIPI SoundWire-I3S
  • Simulation VIP for MIPI SoundWire
    • Multi-lane Payload Transport
    • Up to 8 data lanes are supported
    • High-PHY Mode
    • High-performance PHY
    Block Diagram -- Simulation VIP for MIPI SoundWire
  • MIPI SoundWire I3S Verification IP
    • Full MIPI SoundWire I3S Master, Slave and Monitor functionality
    • Supports MIPI Soundwire-I3S Bus Draft Specification v0.4r06.
    • Supports system with one master and one or more slaves (upto 8 slaves).
    • Supports LVDS PHY for higher speed and a single-ended CMOS PHY for lower speed systems.
    Block Diagram -- MIPI SoundWire I3S Verification IP
  • MIPI SoundWire Verification IP
    • Full MIPI SoundWire Master, slave and Monitor functionality
    • Supports MIPI SoundWire version 1.2r08 Specifications
    • Supports Basic PHY and High PHY mode
    • Supports IO timing
    Block Diagram -- MIPI SoundWire Verification IP
  • MIPI SOUNDWIRE Synthesizable Transactor
    • Supports MIPI SoundWire version 1.2r08 Specifications
    • Supports full MIPI SoundWire Master,Slave functionality
    • Supports Basic PHY and High PHY mode
    • Supports IO timing
    Block Diagram -- MIPI SOUNDWIRE Synthesizable Transactor
  • MIPI SOUNDWIRE PSVIP
    • Supports MIPI SoundWire version 1.2r08 Specifications
    • Supports full MIPI SoundWire Master,Slave functionality
    • Supports Basic PHY and High PHY mode
    • Supports IO timing
    Block Diagram -- MIPI SOUNDWIRE PSVIP
  • MIPI SOUNDWIRE SLAVE IIP
    • Compliant with MIPI SOUNDWIRE version 1.1x Specification.
    • Full MIPI SOUNDWIRE Slave functionality
    • Supports slave-to-slave transport.
    • Supports upto 8 data lanes.
    Block Diagram -- MIPI SOUNDWIRE SLAVE IIP
×
Semiconductor IP