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MIPI I3C IP

MIPI I3C® IP is a scalable, medium-speed, utility and control bus interface for connecting peripherals to an application processor, streamlining integration and improving cost efficiencies. It gives developers unprecedented opportunities to craft innovative designs for any mobile product—from smartphones, to wearables, to systems in automobiles.

Designed as the successor of I2C, MIPI I3C incorporates key attributes of the traditional I2C and SPI interfaces to provide a unified, high-performing, very-low-power solution and delivers a robust, flexible upgrade path to I3C for I2C and SPI implementers. While I3C v1.0 delivered new capabilities to integrate mechanical, motion, biometric, environmental and any other type of sensor, updates to the specification have added new features for peripheral command, control and communication to a host processor over a short distance and system manageability.

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Compare 65 MIPI I3C IP from 18 vendors (1 - 10)
  • MIPI I3C Total IP Solution
    • The MIPI I3CⓇ Total IP solution is a seamless integration of MIPI I3CⓇ controller, MIPI I3CⓇ PHY I/O, and MIPI I3CⓇ software stack.
    • The MIPI I3CⓇ Total IP solution is a simplified, backward compatible with I2C, scalable, and cost-effective interface.
    Block Diagram -- MIPI I3C Total IP Solution
  • I3C PHY
    • The I3C bus is used for various sensors in the mobile/automotive system where the Host transfers data and control between itself and various sensor devices.
    • The I3C interface is intended to improve upon the features of the I2C interface, preserving backward compatibility.
    Block Diagram -- I3C PHY
  • I3C Host Controller IP v1.2
    • The I3C Host Controller IP implements Host Controller functionality as defined by the MIPI Alliance’s I3C Specification.
    • The I3C bus is used for various sensors in the mobile/automotive system where the Host Controller transfers data and control between itself and various sensor devices.
    • The I3C Host Controller IP Core provides a 32-bit AHB bus as the application interface to configure and control the I3C Host Controller IP Core.
    Block Diagram -- I3C Host Controller IP v1.2
  • I3C Dual/Secondary Controller IP v1.2
    • The I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specification and Secondary Controller logic. 
    • The I3C bus is used for various sensors in the mobile/automotive system where the active controller transfers data and control between itself and various sensor devices. 
    Block Diagram -- I3C Dual/Secondary Controller IP v1.2
  • I3C Dual/Secondary Controller IP
    • Overview
    • The Arasan I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specification and Secondary Controller logic.  The I3C bus is used for various sensors in the mobile/automotive system where the active controller transfers data and control between itself and various sensor devices.  In some applications, the active controllers can handoff the controller role to the secondary controller on the bus. The Dual role IP joins the I3C bus as a secondary controller (as a target) and will request/accept the controller role.  The IP core provides a 32bit AHB bus as application interface to configure and control the transfers.  The controller manages the control signal to IO buffers during the active and standby mode.  Please note that the User needs to provide appropriate IO buffers to meet the I3C specification.
    • The I3C Dual Controller implements support for legacy I2C Slave devices, Clock frequency scaling, Open-drain and Push-pull operation of I3C Interface, and Dynamic Addressing support. The I3C Dual Controller supports the required SDR mode with Clock frequency of up to 12.5 MHz and also the HDR mode (HDR-DDR) as defined by the I3C Specification.
    Block Diagram -- I3C Dual/Secondary Controller IP
  • I3C Device Controller IP v1.2
    • The I3C Device Controller IP Implements Device Controller functionality as defined by the MIPI Alliance’s I3C Specification. 
    • The I3C bus is used for various sensors in the mobile/automotive system where an I3C Host Controller transfers data and control information between itself and various sensor devices.
    Block Diagram -- I3C Device Controller IP v1.2
  • I3C 1.1 Host Controller
    • The I3C Host Controller IP implements Host Controller functionality as defined by the MIPI Alliance’s I3C Specification.
    • The I3C bus is used for various sensors in the mobile/automotive system where the Host Controller transfers data and control between itself and various sensor devices.
    • The I3C Host Controller implements support for legacy I2C Device Controllers, Clock frequency scaling, Open-drain and Push-pull operation of I3C Interface, and Dynamic Addressing support.
    Block Diagram -- I3C 1.1 Host Controller
  • I3C 1.1 Device Controller
    • The I3C Device Controller IP Implements Device Controller functionality as defined by the MIPI Alliance’s I3C Specification.
    • The I3C bus is used for various sensors in the mobile/automotive system where an I3C Host Controller transfers data and control information between itself and various sensor devices.
    • The I3C Device Controller IP can be easily integrated into the Sensor/Device Controllers with minimal gate count.
    Block Diagram -- I3C 1.1 Device Controller
  • I3C - Function Controller
    • The I3c protocol, short for " Improved Inter - Integrated Circuit," is a communication protocol designed to improve upon the widely - used I2C protocol.
    • It was developed by the MIPI Alliance, a global organization that aims to develop interface specifications for mobile devices.
    Block Diagram -- I3C - Function Controller
  • MIPI I3C Master RISC-V based subsystem
    • RISC-V based MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a fast, low cost, low power, two-wire digital interface for sensors
    • All the basic functionalities of MIPI I3C master has been proved with Microsemi smart fusion 2 creative development board .In addition the MIPI I3C master supports for both AHB lite and APB Interface
    Block Diagram -- MIPI I3C Master RISC-V based subsystem
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