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MIPI SLIMbus IP

The MIPI SLIMbus controller IP cores are designed to provide MIPI SLIMbus1.01 compliant connectivity for a peripheral device. The MIPI SLIMbus® specification supports a wide range of digital audio and control solutions to seamlessly transport audio and related data for larger-sized mobile device components such as the application processor, audio codec, modem, audio digital signal processor, Bluetooth chipset and FM receiver. Multiple components can be interconnected on the same link to lower overall system costs and facilitate flexible designs.

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Compare 7 MIPI SLIMbus IP from 3 vendors (1 - 7)
  • SLIMbus Host IP V2.0
    • The MIPI SLIMbus Host v2.0 typically resides in a mobile platform’s application processor and provides two-wire, multipurpose connectivity with multiple audio and another low/mid bandwidth peripheral devices.
    • The SLIMbus Host Controller IP is designed to provide MIPI SLIMbus 2.0 compliant connectivity to an SoC.
    Block Diagram -- SLIMbus Host IP V2.0
  • SLIMbus Device IP Core
    • The SLIMbus v2.0 Device Controller IP is designed to provide MIPI SLIMbus compliant connectivity for a peripheral device, like an audio codec, to a SLIMbus compliant host, like an Applications Processor on a mobile platform, and share the bus bandwidth with other SLIMbus devices that may exist.
    Block Diagram -- SLIMbus Device IP Core
  • MIPI SLIMbus Software Stack
    • Compliant with MIPI SLIMbus® Specification version 1.01
    • Portability in choice of OS, processors and hardware
    • Easy-to-use interface for applications
    • Fully documented generic interface API
    Block Diagram -- MIPI SLIMbus Software Stack
  • MIPI SLIMbus Hardware Validation Platform
    • The SLIMbus® (Serial Low-power Inter-chip Media bus protocol) Hardware Validation Platform provides the mobile industry a versatile means to assist in the development and debugging of SLIMbus® products.
    • By emulating a real-world SLIMbus host component, this platform can be used by system and software developers to completely validate the implementation of the SLIMbus interface in their products during various stages of the development cycle.
    Block Diagram -- MIPI SLIMbus Hardware Validation Platform
  • Simulation VIP for MIPI SLIMbus
    • Segment distribution
    • SLIMbus v2.0: Supports all segment distribution codes.
    • Multichannel stream
    • SLIMbus v2.0: Supports data carrying on multiple channels that have the same direction and sample rate and that are phase-aligned.
    Block Diagram -- Simulation VIP for MIPI SLIMbus
  • MIPI SLIMBUS Verification IP
    • Supports 1.01.01/2.0 MIPI SLIMbus Specification.
    • Supports Organized TDM frame structure allows SLIMbus to carry Control and Data information.
    • Supports unidirectional CLK line.
    • Supports up to 8 bi-directional data line.
    Block Diagram -- MIPI SLIMBUS Verification IP
  • MIPI SLIMBUS Synthesizable Transactor
    • Supports 1.01.01/2.0 MIPI SLIMbus Specification
    • Supports organized TDM frame structure which allows SLIMbus to carry Control and Data information
    • Supports unidirectional CLK line
    • Supports up to eight bi-directional DATA line
    Block Diagram -- MIPI SLIMBUS Synthesizable Transactor
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