Die to Die IP
Welcome to the ultimate Die to Die IP hub! Explore our vast directory of Die to Die IP.
A die-to-die IP is a functional block that provides the data interface between two silicon dies that are assembled in the same package. Die-to-die interfaces take advantage of very short channels to connect two dies inside the package to achieve power efficiency and very high bandwidth efficiency, beyond what traditional chip-to-chip interfaces achieve.
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Die to Die IP
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91
Die to Die IP
from 17 vendors
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10)
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
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UCIe Die-to-Die Controller IP
- High Configurability and Customizability
- Comprehensive Verification
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2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- Efficiency
- Composability
- Programmability
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Universal Chiplet Interconnect Express (UCIe 1.0) Controller
- Package Flexibility
- Power Efficiency
- Low Latency
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Ultralink Controller
- 1Tbps/mm unidirectional bandwidth
- Low power and low latency
- Easy routing and straightforward integration
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UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
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D2D UCIe 1.1
- Compatible with UCIe v1.1 specification
- Features single-ended, source-synchronous, and DDR I/O signaling
- Supports 32-bit (16-bits TX + 16-bit RX) data bus per module for standard packages
- Offers a high clock frequency up to 16GHz
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Die-to-Die, High Bandwidth Interconnect PHY Ported to TSMC N7 X24
- Delivers up to 4Gbps per pin with up to bidirectional 2 Tbps/mm of die edge
- High-bandwidth, low-power, low-latency multi-channel PHY in applications requiring connections between dies within a package
- Compliant with Intel Advanced Interface Bus (AIB) v1.1 standard
- Compliant with IEEE 1149.1 (JTAG), 1149.6 (AC JTAG) for easy integration with SoC testability framework
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Die-to-Die, High Bandwidth Interconnect PHY Ported to TSMC N5 X24, North/South (vertical) poly orientation
- Delivers up to 4Gbps per pin with up to bidirectional 2 Tbps/mm of die edge
- High-bandwidth, low-power, low-latency multi-channel PHY in applications requiring connections between dies within a package
- Compliant with Intel Advanced Interface Bus (AIB) v1.1 standard
- Compliant with IEEE 1149.1 (JTAG), 1149.6 (AC JTAG) for easy integration with SoC testability framework
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Die-to-Die, AIB 2.0 PHY Ported to Intel 16, North/South (vertical) poly orientation
- Delivers up to 4Gbps per pin with up to bidirectional 2 Tbps/mm of die edge
- High-bandwidth, low-power, low-latency multi-channel PHY in applications requiring connections between dies within a package
- Compliant with Intel Advanced Interface Bus (AIB) v1.1 standard
- Compliant with IEEE 1149.1 (JTAG), 1149.6 (AC JTAG) for easy integration with SoC testability framework
