The UCIe Verification IP provides an effective & efficient way to verify the UCIe components of an IP or SoC. The VIP is fully compliant with UCIe Specification version 1.1. The VIP is light weighted with easy plug-andplay components so that there is no hit on the design
UCIe Verification IP
Overview
Benefits
- Available in native SystemVerilog (UVM/OVM /VMM) and Verilog.
- Unique development methodology to ensure highest levels of quality.
- Availability of various Regression Test Suites.
- 24X5 customer support.
- Unique and customizable licensing models.
- Exhaustive set of assertions and cover points with connectivity example for all the components.
- Consistency of interface, installation, operation and documentation across all our VIPs.
- Provide complete solution and easy integration in IP and SoC environment.
Block Diagram
