Peripheral IP for UMC

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Compare 26 Peripheral IP for UMC from 8 vendors (1 - 10)
  • PCIe 3.1 Controller with AXI
    • Compliant with the PCI Express 3.1/3.0, and PIPE (16- and 32-bit) specifications
    • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    • Supports Endpoint, Root-Port, Dual-mode configurations
    • Supports x16, x8, x4, x2, x1 at 8 GT/s, 5 GT/s, 2.5 GT/s speeds
    • Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
    • Supports many ECNs including LTR, L1 PM substates, etc.
    Block Diagram -- PCIe 3.1 Controller with AXI
  • 15 to 2780 kHz amplifier with band-pass filter
    • UMC CMOS 0.18 um
    • Low consuming
    • Wide gain adjustment range
    • Differential input and output
    Block Diagram -- 15 to 2780 kHz amplifier with band-pass filter
  • PowerPC System Controller
    • Designed for ASIC and PLD implementations.
    • Fully static design with edge triggered flip-flops.
    • Supports PowerPC 603, 604, 740, 750, MPC8260, 860 microprocessors.
    • Fully integrated single chip design provide complete system level functions for all external data access.
    Block Diagram -- PowerPC System Controller
  • Minimum-area low-power clocking PLL (1st gen)
    • - Super small: 80 x 80 microns!
    • - Very low power: 12-mW
    • - Broad frequency range: 2-GHz
    • - Fast lock
    Block Diagram -- Minimum-area low-power clocking PLL (1st gen)
  • General Purpose Input/Output Controller
    • AMBA AXI4-Lite bus
    • Individual configuration of each GPIO pin
    • Dynamic programming of each GPIO pin as input or output
    • Configurable level or edge triggered interrupts
    Block Diagram -- General Purpose Input/Output Controller
  • General Purpose Input/Output Controller
    • AMBA APB3 bus
    • Individual configuration of each GPIO pin
    • Dynamic programming of each GPIO pin as input or output
    • Configurable level or edge triggered interrupts
    Block Diagram -- General Purpose Input/Output Controller
  • Configurable Watchdog Timer
    • AMBA APB4-Lite bus
    • Configurable timeout interval
    • Standard and windowed mode
    • Register write protection
    Block Diagram -- Configurable Watchdog Timer
  • Configurable Watchdog Timer
    • AMBA APB3 bus
    • Configurable timeout interval
    • Standard and windowed mode
    • Register write protection
    Block Diagram -- Configurable Watchdog Timer
  • Configurable System Tick Counter
    • AMBA APB4-Lite bus
    • Programmable system tick timer
    • Configurable prescaler and period
    • Configurable interrupts
    Block Diagram -- Configurable System Tick Counter
  • Configurable System Tick Counter
    • AMBA APB3 bus
    • Programmable system tick timer
    • Configurable prescaler and period
    • Configurable interrupts
    Block Diagram -- Configurable System Tick Counter
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