Configurable Timer Counter

Overview

The CC-TIMER-AXI is a synthesisable Verilog model of a timer counter controller. The TIMER core can be efficiently implemented on FPGA and ASIC technologies.

Key Features

  • AMBA AXI4-Lite bus
  • Programmable multi-function timer
  • Double buffered configuration registers
  • Configurable single/dual slope PWM outputs
  • Configurable standard/period/pulse input capture mode
  • Stop in debug mode option
  • Fully synthesizable synchronous design with positive edge clocking
  • DFT ready

Benefits

  • Synthesizable RTL Verilog source code
  • Technology independent IP Core
  • Suitable for FPGA and ASIC
  • Silicon and FPGA proven
  • Easy SoC integration
  • Full implementation and maintenance support with individual approach
  • Flexible licensing scheme

Block Diagram

Configurable Timer Counter Block Diagram

Deliverables

  • Verilog RTL source code
  • Verification suite
  • Datasheet and integration guide
  • C-header file
  • Constraints
  • Technical support

Technical Specifications

Availability
Now
UMC
Silicon Proven: 130nm
×
Semiconductor IP