IP Catalog > Foundries > UMC > Memory & Libraries IP > I/O Library IP

I/O Library IP for UMC

Welcome to the ultimate I/O Library IP for UMC hub! Explore our vast directory of I/O Library IP for UMC
All offers in I/O Library IP for UMC
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (419)
Compare 419 I/O Library IP for UMC from 8 vendors (1 - 10)
  • LVDS Deserializer IP
    • The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
    • Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
    Block Diagram -- LVDS Deserializer IP
  • 5MHz-35MHz Low Power Crystal Oscillator - TSMC 0.18µ
    • 4MHz-35MHz Frequency range.
    • No external bias or limit resistors required.
    • Current optimization for best power at frequency.
    • Amplitude control loop.
    • The OSCI pad input can be used as a CMOS input for test.
    • Uses single 1.8V supply.
    • Enable/power down provision.
    Block Diagram -- 5MHz-35MHz Low Power Crystal Oscillator - TSMC 0.18µ
  • LVDS interfaces
    • Wide operating range
    • High data rates
    • Very flexible programmability
    • Excellent signal integrity
    • TIA/EIA644A LVDS and sub-LVDS compatibility
    • Receiver also compatible with LVPECL
    Block Diagram -- LVDS interfaces
  • Camera 6/7-mode Combo Receiver - 1G/1.5Gbps
    • The CL12684KM4-8-12-16R3AM6-7ZIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
    • The CL12684KM4-8-12-16R3AM6-7ZIP is designed to support data rate in excess of maximum 1Gbps utilizing sub-LVDS / mini-LVDS / LVDS / HiSPi(SLVS-400, HiVCM) / MIPI-DPHY / CMOS-1.8V / CMOS-3.3V interface specification.
  • LCD Host LVDS Interface, Dual Pixel 20-112Mhz (SVGA/QXGA)
    • 1P6M layout structure based on 0.18um 1P6M 1.8V generic logic process.
    • 3.3V/1.8V ±10% supply voltage, -40/+125°C
    • Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
    • Up to 5.38Gbps bandwidth
  • 7 way DDR combo
    • Full DDR4 capability
    • Full DDR3 / DDR3L / DDR3U capability
    • Full LPDDR4 capability
    • Full LPDDR3 capability
  • FPD-link, 30-Bit Color LVDS Receiver, 20-112Mhz
    • 1P7M/1P8M/1P9M/1P10M layout structure based on 65nm Logic 1P10M Salicide 1.2V/2.5V process.
    • 1.2V/2.5V ±10% supply voltage, -40/+125°C
    • Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
    • Up to 3.92Gbps bandwidth (20 to 112Mhz pixel clock)
  • Dual RSDS Transmitter, 30-bit color, 80-400Mb/s (SVGA/Full HDTV@120Hz)
    • • 40 to 200 Mhz Pixel rate per channel ( 80 to 400 Mb/s SDR input, 80 to 400 Mb/s DDR output)
    • • 30 DATA + 9 RSDS CLK channels
    • • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
    • • 1P6M layout structure based on 0.13um 1P6M generic logic process.
  • Dual RSDS Transmitter, 30-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display
    • • 20 to 150 Mhz Pixel rate per channel ( 40 to 300 Mb/s SDR input, 40 to 300 Mb/s DDR output )
    • • 30 DATA + 9 RSDS CLK channels
    • • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
    • • 1P6M layout structure based on 0.18um 1P6M generic logic process.
  • FPD-link, 30Bits Color LVDS Receiver, 150Mhz (SVGA/WXGA)
    • 1P6M layout structure based on 0.18um 1P6M 1.8V generic logic process.
    • 3.3V/1.8V 10% supply voltage, 0/+125C
    • Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
    • Up to 3.15Gbps bandwidth (8 to 90Mhz pixel clock for 1 channel)
×
Semiconductor IP