Interface IP for UMC
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Interface IP
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367
Interface IP
for UMC
from 23 vendors
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125Mbps to 16Gbps Multi-protocol SerDes PMA
- Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
- Extremely low jitter suitable for Enterprise SerDes applications
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250Mbps to 12.7Gbps Multiprotocol SerDes PMA
- Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
- Extremely low jitter suitable for Enterprise SerDes applications
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Complete USB Type-C Power Delivery PHY, RTL, and Software
- USB PD 3.1 compliant.
- 8 bit register interface for a low speed processor, or optional I2C interface.
- Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
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MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI Specification for D-PHY Version 1.2
- Supports MIPI Specification for C-PHY Version 1.0
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PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- Supports 2.5Gb/s serial data rate
- Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
- Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
- Data and clock recovery from serial stream on the PCI Express bus
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I2C Master Serial Interface Controller
- I2C-compatible interface
- AMBA AXI4-Lite bus
- Standard and custom data rates
- Configurable setup/hold times
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I2C Master Serial Interface Controller
- I2C-compatible interface
- AMBA APB3 bus
- Standard and custom data rates
- Configurable setup/hold times
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MIPI D-PHY Universal IP in UMC 40LP
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports the MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
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HDMI 2.0 TX PHY 6Gbps in UMC 28HPC 1.8V, North/South Poly Orientation
- Support for key HDMI 2.0 features such as 4Kx2K resolution at 60 Hz frame rate, YCbCr 4:2:0 pixel encoding format, TMDS scrambling, High Dynamic Range (HDR), CEC 2.0, and 18.0 Gbps aggregate bandwidth
- Compliant with HDMI 2.0 and HDCP 2.3, 1.2 specification
- Optimized for low power and small area
- Timing hardened blocks enable simplified placement and design closure
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DDR4 multiPHY - UMC 28HPC18
- Support for JEDEC standard DDR4, DDR3, LPDDR2, and LPDDR3 SDRAMs
- Scalable architecture that supports data rates up to DDR4-2667
- Support for DIMMs
- Delivery of product as a hardened mixed-signal macrocell component allows precise control of timing critical delay and skew paths
