Clock Synthesizer IP for UMC

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All Digital Fractional-N PLL for Performance Computing in UMC 40LP
- Fractional multiplication with frequency up to 4GHz
- Low jitter (< 10ps RMS)
- Small size (< 0.01 sq mm)
- Low Power (< 5mW)
Fractional-N Frequency Synthesizer (40nm - 110nm)
- Fractional/Integer-N frequency synthesizing.
- Spread spectrum clock generation (SSCG) function. (TSMC 40nm (CLN40ULP), UMC 55nm(LP) only)
Input 2MHz~16MHz, output 16~1000MHz, 1.08~1.32V small-size PLL; UMC 55nm Eflash Process.
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process
NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm EFLASH process. _x005F_x000D_
Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process
Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process.
IP name: FXS2D101HH0L Area: 300um*300um

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