Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process.

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Technical Specifications

Foundry, Node

UMC 40nm Logic/Mixed_Mode LP

UMC

Pre-Silicon: 40nm , 40nm LP

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