ADC / DAC IP for UMC

Compare 128 ADC / DAC IP for UMC from 8 vendors (1 - 10)

2-bit 2-channel 50 MSPS flash ADC
- UMC CMOS 180 nm
- Resolution 2-bit
- Adjustment of threshold levels
- Adjustment of dc level of thresholds scale
2-bit 2-channel 100 MSPS flash ADC
- UMC CMOS 180 nm technology
- Resolution 2 bit
- Adjustment of threshold levels
- Adjustment of dc level of thresholds scale
12-bit single-ended SAR ADC
- Sample rate 200 kHz
- Unipolar, Single-ended input range: 0V to 1.2V
Dual 12-Bit 20 to 200MS/s 1.2V ADC, CMOS 90nm
- TSMC 90nm general purpose 1.2V CMOS process
- Single 1.2V supply
- 20 to 200 Mspls/s scalable sampling rate
- 0.5 Vp_diff input dynamic range
10-Bit 100MS/s 1.8V 66mW ADC, CMOS 0.18µm
- UMC 180nm 1.8V CMOS process with MIM capacitors (optional)
- Single 1.8V supply
- up to 100 Mspls/s sampling rate
- 2Vpp_diff input dynamic range
Pipeline ADC
Low power 9 bit cyclic ADC
- Low power consumption
- Insensitivity to power supply variations
12-Bit High-Performance DAC for 802.11ac
- Integrated voltage reference
- Standard CMOS implementation
- Yield enhanced
12-Bit High-Performance Pipelined ADC for 802.11ac
- Integrated voltage reference
- Standard CMOS implementation
- Yield enhanced
Triple HD-video AFE digitizer - 10bits/170Mhz - 8bits/205Mhz
- Triple channel video 10bits digitizer 170Mhz
- 0.5 to 1V analog input range
- 3.3V/1.8V ±10% supply voltage, -40/+125°C
- 1P6M layout structure based on 0.18um 1P6M 3.3V/1.8V generic logic process.