Dual 12-Bit 20 to 200MS/s 1.2V ADC, CMOS 90nm
Overview
The nSAD_TS90GP_1V2_AD2x12b200M is a dual 200MS/s, 11 ENOB, dual pipeline AD converter designed on the TSMC 90 GP technology. Built around a fully-differential pipeline converter and a digital error correction circuitry, it consumes 140mW on silicon, reaching an energy efficiency of 340fJ/conversion-step. A low noise input buffer is provided for easier interfacing with your analog/RF front-end.
Key Features
- TSMC 90nm general purpose 1.2V CMOS process
- Single 1.2V supply
- 20 to 200 Mspls/s scalable sampling rate
- 0.5 Vp_diff input dynamic range
- Up to 100MHz input buffer signal bandwidth
- DNL = ±0.5 LSB typ., INL = ±1 LSB typ.
- SNR = 68dBFS @ Fin = 10MHz and 200MS/s
- SFDR > 72dBc @ Fin = 10MHz and 200MS/s
- Fully internal reference voltage generator and bias circuitry. No external decoupling needed.
- Proprietary architecture enhancements allowing very high conversion efficiency
- less than 1.3 mm2 core area including two input buffers, the reference generator, biasing and internal decoupling
- Power down mode
Block Diagram
Technical Specifications
Foundry, Node
TSMC 90nm GP
Maturity
In design
TSMC
Pre-Silicon:
90nm
LP
UMC
Pre-Silicon:
90nm
G