Analog IP for UMC

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Compare 1,204 Analog IP for UMC from 20 vendors (1 - 10)
  • 5MHz-35MHz Low Power Crystal Oscillator - TSMC 0.18µ
    • 4MHz-35MHz Frequency range.
    • No external bias or limit resistors required.
    • Current optimization for best power at frequency.
    • Amplitude control loop.
    • The OSCI pad input can be used as a CMOS input for test.
    • Uses single 1.8V supply.
    • Enable/power down provision.
    Block Diagram -- 5MHz-35MHz Low Power Crystal Oscillator - TSMC 0.18µ
  • UMC 55nm ULP Bandgap / Current Reference
    • 3σ 4% untrimmed voltage reference accuracy.
    • 1% variation over -40ºC to 125ºC after trimming.
    • 70dB low frequency PSRR.
    • Trimmed, temperature compensated, 10µA reference current outputs with 3% accuracy.
    • Trimmed IPTAT output currents can be provided.
    • Less than 8µV noise from 0.1Hz to 10KHz.
    Block Diagram -- UMC 55nm ULP Bandgap / Current Reference
  • Process/Voltage/Temperature Sensor (Supply voltage 1.8V/0.9V)
    • UMC 28nm HPC+ technology
    • Temperature measurement range -40°C ÷ +125°C
    • Core and IO Voltage measurement range: 0.58V÷0.92V, 1.0V÷2.0V, 1.5V÷3.63V and 0.8÷3.63V
    • High accuracy temperature and voltage measurements
    Block Diagram -- Process/Voltage/Temperature Sensor (Supply voltage 1.8V/0.9V)
  • Phase-locked loop frequency synthesizer
    • CMOS UMC 65 nm
    • Integer-N frequency synthesizer with good phase noise performance
    • Guaranteed frequency range 550…750 MHz
    • Wide continuous loop frequency divider ratio range (16..2047 with step 1) allow to cover frequency range using different reference frequency
    Block Diagram -- Phase-locked loop frequency synthesizer
  • Sleep Management Subsystem
    • Power-On-Reset
    • Programmable relaxation oscillator
    • Low Power Comparator
    Block Diagram -- Sleep Management Subsystem
  • Sensor Interface Subsystem
    • The agileSensorIF Subsystem is an efficient and highly integrated sensor interface for SoCs/ASICs.
    • Featuring multiple Analog-to-Digital Converters (agileADC), Digital-to-Analog Converters (agileDAC), low-power programmable analog comparators (agileCMP_LP), and an associated reference generator (agileREF).
    • The agileSensorIF Subsystem enables easy interaction with the analog world.  
    Block Diagram -- Sensor Interface Subsystem
  • Free running oscillators
    • Compact and low power
    • No external components
    • Baseline CMOS logic process masks only
    • Excellent frequency precision over PVT after trimming
    Block Diagram -- Free running oscillators
  • 2-bit 2-channel 50 MSPS flash ADC
    • UMC CMOS 180 nm
    • Resolution 2-bit
    • Adjustment of threshold levels
    • Adjustment of dc level of thresholds scale
    Block Diagram -- 2-bit 2-channel 50 MSPS flash ADC
  • 2-bit 2-channel 100 MSPS flash ADC
    • UMC CMOS 180 nm technology
    • Resolution 2 bit
    • Adjustment of threshold levels
    • Adjustment of dc level of thresholds scale
    Block Diagram -- 2-bit 2-channel 100 MSPS flash ADC
  • 10MHz to 50MHz fractional-N PLL synthesizer
    • UMC 22nm ULP technology
    • 1.8V IO power supply
    • Double 0.8/1.0V Core power supply
    • Embedded low noise bias
    Block Diagram -- 10MHz to 50MHz fractional-N PLL synthesizer
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