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Interface Security IP for TSMC

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Compare 8 Interface Security IP for TSMC from 2 vendors (1 - 8)
  • Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
    • One input word per clock without any backpressure
    • Design can switch stream, algorithm, mode, key and/or direction every clock cycle
    • GCM: throughput is solely determined by the data width, data alignment and clock frequency
    • XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
    Block Diagram -- Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
  • 800G Multi-Channel MACsec Engine with TDM Interface
    • Complete and fully compliant MACsec Packet Engine with classifier and transformation engines for rates of 100 to 800 Gbps, up to 64 channels, ready for FlexE
    • All IEEE MACsec standards supported (including IEEE802.1AE-2018). Optional inclusion of Cisco extensions, IPsec ESP tunnel and transport mode with AES-GCM cipher
    • Supplied with the Driver Development Kit to accelerate time to market. Rambus offers MACsec Toolkit for IEEE 802.1X key management
    Block Diagram -- 800G Multi-Channel MACsec Engine with TDM Interface
  • Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
    • Protocol aware IPsec, SSL, TLS, DTLS, 3GPP and MACsec Packet Engine with virtualization, caches classifier and Look-Aside interface for multi-core application processors
    • 5-10 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, AMBA interface
    • Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP, DPDK, Linux Crypto
    Block Diagram -- Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
  • Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
    • Protocol aware IPsec, SSL, TLS, DTLS, 3GPP, MACsec packet engine with classifier and in-line interface for multi-core server processors
    • 10-100 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, streaming and AMBA interface
    • Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP.
    Block Diagram -- Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
  • Multi-Protocol Engine, Look-Aside, 1 Gbps
    • Protocol-aware IPsec/TLS packet engine with Look-Aside interface for IoT.
    • Up to 1 Gbps, lowest gate count in the industry, just 100K gates (ex AMBA interface).
    • Supported by Driver Development Kit, QuickSec IPsec toolkit, Secure Boot Toolkit.
    Block Diagram -- Multi-Protocol Engine, Look-Aside, 1 Gbps
  • MACsec 10G/25G
    • Compliance with IEEE Std 802.1AE-2018
    • Line-rate traffic encryption and decryption
    • Supports 10G/25G data rates
    • Multiple Connectivity Associations (SecYs) with Traffic Mapping Rules
    Block Diagram -- MACsec 10G/25G
  • 1G to 50G Single-Port MACsec Engine with TSN support
    • Complete and compliant MACsec Packet Engine for rates from 1GbE to 50GbE with TSN support (including IEEE803.2br).
    • All IEEE MACsec standards supported (incl. IEEE802.1AE-2018). Optional Cisco ClearTags.
    • Supplied with the Driver Development Kit to accelerate time to market. Rambus offers MACsec Toolkit for IEEE 802.1X key management
  • In-line Multi-Protocol Cipher Engine
    • IPSec (IPv4 and IPv6):
    • and 6379),
    • MACsec
    • 802.1AE
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