1G/2.5G/5G/10G/25G/50G MACsec

Overview

Flexible and Silicon proven  Ethernet Layer 2 Security solution

The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE. It protects components in Ethernet networks especially high-speed Ethernet used in automotive, industrial, cloud, data center, and wireless infrastructure. The MACsec IP is a fully compliant solution that provides line-rate encryption and supports VLAN-in-Clear.

The MACsec core is configurable to have multiple Security Entities, SecYs, in a single IP to support multiple Connectivity Associations per port for traffic differentiation, and is prepared for easy interfacing with Comcores or third-party MAC, PCS and TSN Switch IPs. It implements 8-bit or 64-bit AXI-S input and output data interfaces, and can be delivered with (X)GMII interfaces for placement below the MAC. It offers flexibility on integration with IEEE 1588 PTP Timestamping Unit (TSU). It additionally includes a software tool for MACsec Key Agreement Protocol IEEE 802.1X integration.

Key Features

Delivers Performance

  • Compliance with IEEE Std 802.1AE-2018
  • Line-rate traffic encryption and decryption
  • Optimized for area and latency

Highly Configurable

  • Supports 1G / 2.5G / 5G / 10G / 25G / 50G data rates
  • Multiple Connectivity Associations (SecYs) with Traffic Mapping Rules
  • Multiple integration context for placement above or below the MAC
  • Optional PTP-TSU for IEEE 1588 PTP packets protection

Feature Rich

  • AES-GCM-128 and AES-GCM-256 Cipher Suites
  • VLAN-in-Clear
  • Confidentiality Offset
  • Software tool for MACsec Key Agreement Protocol IEEE 802.1X integration

Silicon Agnostic

  • Designed in Verilog and targeting both ASICs and FPGAs

Block Diagram

1G/2.5G/5G/10G/25G/50G MACsec Block Diagram

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual and Release Note
  • Simulation Environment, including Simple Testbed, Test case and Test Script
  • Programming Register Specification
  • Timing Constraints in Synopsys SDC format
  • Access to support system and direct support from Comcores Engineers
  • Synopsys SGDC Files (optional)
  • Synopsys Lint, CDC and Waivers (optional)

Technical Specifications

Short description
1G/2.5G/5G/10G/25G/50G MACsec
Vendor
Vendor Name
Availability
Available
TSMC
Silicon Proven: 7nm , 16nm , 28nm , 40nm G
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Semiconductor IP