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Video Codec IP for TSMC

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Search (15)
Compare 15 Video Codec IP for TSMC from 6 vendors (1 - 10)
  • SLVS-EC TX PHY - 10GBPS 8-Lane - TSMC 12FFC
    • SLVS-EC ver.3.0 compliant
    • Data Rate: Up to 10Gbps / lane
    • Number of data lane: 8
    • Support input clock: 24MHz, 54MHz, 37.125MHz, 72MHz, 74.25MHz
    Block Diagram -- SLVS-EC TX PHY - 10GBPS 8-Lane - TSMC 12FFC
  • Camera Receiver - 10.0Gbps 8-Lane - TSMC 12FFC
    • The CL12812M8RIP10000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP.
    • The CL12812M8RIP10000 is designed to support data rate in excess of maximum 10Gbps utilizing SLVS-EC ver.3.0 interface specification.
    Block Diagram -- Camera Receiver - 10.0Gbps 8-Lane - TSMC 12FFC
  • LVDS interfaces
    • Wide operating range
    • High data rates
    • Very flexible programmability
    • Excellent signal integrity
    • TIA/EIA644A LVDS and sub-LVDS compatibility
    • Receiver also compatible with LVPECL
    Block Diagram -- LVDS interfaces
  • ISDB-T1, Segment Tuner (470-860MHz UHF)
    • High Performance
    • Configurable 3/4 wire controller
    • Self calibrating and programmable filter corner frequencies
    • 8 Bit electronically tunable tracking filter
    Block Diagram -- ISDB-T1, Segment Tuner (470-860MHz UHF)
  • ITU G.711 expander
    • Expands 8 bit a-law or u-law logarithmic PCM to 13/14 bit linear PCM.
    • Compliant to the ITU G.711 standard.
    • Purely combinational logic RTL implementation.
    • Silicon proven in ASIC and FPGA technologies for a variety of applications.
    Block Diagram -- ITU G.711 expander
  • ITU G.711 compressor
    • Compresses 16-bit linear PCM to 8 bit a-law or u-law logarithmic PCM.
    • Compliant to the ITU G.711 standard.
    • Purely combinational logic RTL implementation.
    • Silicon proven in ASIC and FPGA technologies for a variety of applications.
    Block Diagram -- ITU G.711 compressor
  • Configurable SPDIF-AES3 Transmitter
    • The SPDIF-Tx-Pro (CWda15) is a digital audio transmitter IP core supporting the SPDIF IEC60958 and AES3 standards for PCM audio and the IEC61937 and SMPTE 337M standards for non-PCM (compressed) audio.
    • The core is very configurable allowing many features of the standards to be optionally supported by hardware or software.
  • Configurable SPDIF-AES3 Receiver
    • The SPDIF-Rx-Pro (CWda14) is a digital audio receiver IP core supporting the SPDIF and AES3 and IEC60958 standards and also adds hardware support for the IEC61937 and SMPTE 337M standards for non-PCM (compressed) audio.
    • This purely digital clock and data recovery method dispenses the classical analog PLL at the input reducing the receiver cost.
  • Camera 6/7-mode Combo Receiver - 1G/1.5Gbps
    • The CL12684KM4-8-12-16R3AM6-7ZIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
    • The CL12684KM4-8-12-16R3AM6-7ZIP is designed to support data rate in excess of maximum 1Gbps utilizing sub-LVDS / mini-LVDS / LVDS / HiSPi(SLVS-400, HiVCM) / MIPI-DPHY / CMOS-1.8V / CMOS-3.3V interface specification.
  • Camera Receiver - 5.0Gbps 8-Lane - TSMC 12FFC, 6FFC
    • The CL12812M8RIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP.
    • The CL12812M8RIP5000 is designed to support data rate in excess of maximum 5Gbps utilizing SLVS-EC ver.3.0 BG3 interface specification

     

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