SLVS-EC TX PHY - 10GBPS 8-Lane - TSMC 12FFC

Overview

Key Features

• SLVS-EC ver.3.0 compliant
• Data Rate: Up to 10Gbps / lane
• Number of data lane: 8
• Support input clock: 24MHz, 54MHz, 37.125MHz, 72MHz, 74.25MHz
• Polarity of TX differential output for each data lane is programmable.
• Integrated wide range Phase Lock Loop
• 4-bits programmable level of output differential voltage
• Support BIST function for at-speed loopback test
• Selectable data bus mode, 10-bit, 20-bit and 40-bit

Benefits

• This IP is used as an output interface for CMOS image sensors and bridge chips. It supports the latest SLVS-EC 3.0 standard, and can transfer sensor output data at high speed. We can also supply a link controller upon customer request to realize the customer's system.
• This IP can be implemented in 8-lane units and can be tailored to meet customer specifications.

Block Diagram

Applications

• Camera Application
• Security Camera
• Mobile-Phone Camera
• DSC(Digital Still Camera)
• Medical Camera
• SLR
• 3D Camera
• Camcorder
• ISP(Image Signal Processor)

Deliverables

• Verilog Model (verilog / vcs)
• .db file / .lib(Option) file
• symbol / LVS netlist / Hspice netlist(Option)
• LEF, layer map file, layout technology file
• Layout Verification Report (DRC & LVS), Command file
• Datasheet (This file) /Application Note (Usage connection CIS)
• Packaging and Layout Guideline / PCB Guideline
• Static Delay Analysis (STA) Guideline
• Testing Guideline (Option)
• TX Verilog Model and Test Vector(Option)
• CMOS Image Sensor Verilog Models(Option)
• Link Layer IP(CD12811IP) and FPGA Board(Option)

Technical Specifications