I/O Library IP for TSMC

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Compare 24 I/O Library IP for TSMC from 4 vendors (1 - 10)
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  • 7nm
  • I/O Library
    • Dolphin Technology offers an extensive array of Interface IP, all of whichhasbeen optimized for ultra high performance across all processes supported.
    • Our I/O portfolio includes: Standard I/O (General Purpose I/O or GPIO), Specialty I/O (bus-specific I/O), NAND Flash I/O and DDRx & LPDDRx I/O.
  • ESD Protection
    • ESD Protection:
  • TSMC N7 1.2V/1.8V/2.5V/3.3V General Purpose IO with Failsafe/Fail-Tolerant and with CDM 7A, AG2 Platform
    • Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their SoCs targeting mobile, automotive, and high-performance computing (HPC) applications
    • The IP is silicon-proven and available in several foundries and process technologies from 3nm to 22nm
    • Synopsys GPIO library is designed to support multiple voltages; it offers a complete set of support cells (supply, corner spacers, diode breakers, terminators) required to create complete I/O pad rings for system-on-chips (SoCs)
    • The library is compatible with flip-chip packaging
  • TSMC N7 1.2V/1.8V/2.5V/3.3v General Purpose IO with CDM 7A, AG2 Platform
    • Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their SoCs targeting mobile, automotive, and high-performance computing (HPC) applications
    • The IP is silicon-proven and available in several foundries and process technologies from 3nm to 22nm
    • Synopsys GPIO library is designed to support multiple voltages; it offers a complete set of support cells (supply, corner spacers, diode breakers, terminators) required to create complete I/O pad rings for system-on-chips (SoCs)
    • The library is compatible with flip-chip packaging
  • TSMC N7 1.8V/3.3V I3C with CDM 7A, AG2 Platform
    • Synopsys I3C IO library supports a simplified system of connecting and managing multiple sensors in a device
    • Multiple sensor secondary devices can be controlled by one I3C primary device at a time
    • It offers backward compatibility with I2C legacy devices, is designed for high IO voltage domains and supports low-core voltage domains
    • The I3C incorporates the Schmitt-Trigger function, supports I2C Legacy Fast Mode and FM+ Mode, and includes HBM and CDM ESD protection
  • TSMC N7 1.8V LVDS IO with CDM 7A, AG2 Platform
    • Synopsys Low Voltage Differential Signaling (LVDS) IO library is a high-frequency interface that uses differential signals for data transmission
    • A few typical LVDS IO applications are in display monitors, printers, high-speed clock transfers, and high-speed SERDES
    • Synopsys LVDS IO library is used to build an LVDS-based interface for high-speed interconnect applications
    • This library is designed to optimize IO performance with a core voltage of 0.75 V and supports an IO supply voltage of 1.2V/1.5 V
  • Differential Signal Receiver on TSMC CLN7FF
    • Differential IO clock receiver
    • Single-ended output to chip core
    • AC coupled input structure to allow a wide range of input common mode voltages
    • Wide Ranges of input frequencies up to 2000MHz for diverse clocking needs
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