Serdes IP for TSMC

The ApolloCORE(MR/VSR) Multi-Standard-Serdes (MSS) IP is optimized for Medium Reach (MR) and Very Short Reach (VSR) applications.
It is a highly configurable IP that supports all leading edge NRZ and PAM data center standards from 1Gbps to 112Gbps.

The MXL4254A is a silicon proven Quad Gigabit SerDes implemented in digital CMOS technology. Each of the four channels supports data rate up to 4.25 Gbps.It is compatible with router-backplane links, PCI Express, SATA, RapidIO, 10 Gbps Ethernet (XAUI), FibreChannel, SFI-5, SPI-5, and other communication applications.

Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
Compact form factor – 0.116 mm2 active silicon area per lane including ESD
Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
Minimal latency – 3 UI between parallel transfer and serial transmission

Optimized Performance, Power and Area with Design Agility
Supports full-duplex 1.25 to 225Gbps data rates
Enables 1.6T, 800G, 400G, and 200G Ethernet with a PHY + Controller solution
Supports evolving IEEE 802.3 and OIF-CEI-224G standard electrical specifications
Meets the performance requirements of chip-to-module (VSR), chip-to-chip (MR), and copper/backplane (LR) interconnects

1.25Gbps to 116Gbps flexible data rates allowing simultaneous support of different protocols including Ethernet and OTN
Power optimized for short-reach applications with configurability
Superior bit error rate (BER) with extra performance margin beyond short-reach standard requirements
Beachfront optimized floorplan allows north-south and east-west SoC edge placement
Comprehensive on-chip diagnostic features make system testing and debugging quick and easy
Enables 800Gbps networking with PHY and Controller solutions

Supports over 30 protocols including CEI 6G & 11G SR, MR, LR, Ethernet 10GBASE-X/S/K/R, PCIe Gen1/2/3/4, V-by-One HS/US, CPRI, PON, OTN/OTU, 3GSDI, JESD204A/B/C, SATA1-3, XAUI, SGMII
Programmable (De)Serialization width: 8, 10, 16, 20, 32, or 40 bit
Tx ring PLL includes fractional multiplication, spread spectrum and Jitter Cleaner function for Sync-E and OTU
Core-voltage line driver with programmable pre-and post-emphasis