Multi-Protocol PHY IP for TSMC

Compare 6 Multi-Protocol PHY IP for TSMC from 1 vendors (1 - 6)

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25G PHY, TSMC N6 x2 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
16G LP PHY, TSMC N6 x1, North/South (vertical) poly orientation
- Supports 1.25 to 16 Gbps data rates
- Supports PCI Express,IEEE 802.3, SGMII and QSGMII,SATA, CEI-6G and CEI-11G, Serial Rapid IO (SRIO), CPRI, OBSAI, JESD204B
- Supports x1 to x16 macro configurations
32G PHY in TSMC (16nm, 12nm, N7, N6, N5, N5A, N3E. N3P)
- Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)
- Supports back channel initialization, aggregation, bifurcation, and power management
- Supports both internal and external reference clock connections to the PHY
- Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces
16G PHY in TSMC (28nm, 16nm, 12nm, N7, N6)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
- Supports x1, x2, x4, x8, and x16 hard macro configurations
- Lane margining at the receiver
28G LR Ethernet PHY in TSMC (16nm, N7, N6)
- Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)
- Supports back channel initialization, aggregation, bifurcation, and power management
- Supports both internal and external reference clock connections to the PHY
- Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces
25G PHY in TSMC (16nm, 12nm, N7, N6)
- Includes one, two or four full-duplex transceivers (transmit and receive functions)
- Supports back channel initialization, aggregation, bifurcation, and power management
- Supports both internal and external reference clock connections to the PHY
- Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces