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Interface IP Cores for TSMC

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Compare 112 Interface IP Cores for TSMC from 6 vendors (1 - 10)
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  • 7nm
  • Multi-Standard-Serdes (MSS) IP optimized for Medium Reach (MR) and Very Short Reach (VSR) applications
    • The ApolloCORE(MR/VSR) Multi-Standard-Serdes (MSS) IP is optimized for Medium Reach (MR) and Very Short Reach (VSR) applications.
    • It is a highly configurable IP that supports all leading edge NRZ and PAM data center standards from 1Gbps to 112Gbps.
    Block Diagram -- Multi-Standard-Serdes (MSS) IP optimized for Medium Reach (MR) and Very Short Reach (VSR) applications
  • USB 2.0 PHY
    • Designed to the USB 2.0 specification, and operates at High Speed (480Mbps), Full Speed (12Mbps), and Low Speed (1.5Mbps)
    • Complies with the UTMI v1.05 specification
    • Multiple reference clock supported from 9.6MHz up to 52MHz
    • 8-bit 60MHz and 16-bit 30MHz parallel interfaces
    • Battery Charging Specification v1.2
    Block Diagram -- USB 2.0 PHY
  • 10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
    • Supports USB 3.1, PCIe 3.0/2.0/1.0, DP-TX v1.4/ eDP-TX v1.4b, SATA 3, 10G-KR and SGMII
    • Supports PCIe L1 sub-states
    • Supports SRIS and internal SSC generation
    • Supports internal and external clock sources with clock active detection
    Block Diagram -- 10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
  • 112G-VSR PAM4 SerDes PHY - PPA optimized for short reach connectivity
    • 1.25Gbps to 116Gbps flexible data rates allowing simultaneous support of different protocols including Ethernet and OTN
    • Power optimized for short-reach applications with configurability
    • Superior bit error rate (BER) with extra performance margin beyond short-reach standard requirements
    • Beachfront optimized floorplan allows north-south and east-west SoC edge placement
    • Comprehensive on-chip diagnostic features make system testing and debugging quick and easy
    • Enables 800Gbps networking with PHY and Controller solutions
    Block Diagram -- 112G-VSR PAM4 SerDes PHY - PPA optimized for short reach connectivity
  • MIPI D-PHY
    • Multiple Configurations Possible. TX-only (with integrated PLL), RX-only, and combined TX and RX configurations
    • Complete Function for HS TX/RX, LP TX/RX, and LPCD with automatic termination control for high-speed and low-power modes
    • Integrated BIST Capable of producing and checking PRBS, CRPAT, and CJTPAT
    Block Diagram -- MIPI D-PHY
  • 1G Deep Buffering Memory Ethernet Switch IP Core
    • Delivers Performance
    • Highly Configurable
    • Easy to use
    • Silicon Agnostic
    Block Diagram -- 1G Deep Buffering Memory Ethernet Switch IP Core
  • USB 2.0 femtoPHY - TSMC 7FF18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - TSMC 7FF18 x1, OTG, North/South (vertical) poly orientation
  • USB-C 3.1/DP TX PHY for TSMC N7, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1/DP TX PHY for TSMC N7, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC 7FF x1, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC 7FF x1, North/South Poly Orientation
  • USB-C 3.1/DP TX PHY for TSMC 7FF, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1/DP TX PHY for TSMC 7FF, North/South Poly Orientation
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