MIPI D-PHY

Overview

D-PHY physical layer

The IP for MIPI^® D-PHY^sm integrates a high-speed transmitter/receiver, low-power transmitter/receiver, and low-power contention detector that provide the full function of D-PHY. Our IP has an integrated PPI interface for ease-of-integration with MIPI CSI-2 and DSI controllers.

The IP for MIPI D-PHY provides lane flexibility with a compact and rectangular IP footprint, meeting usage models of modern SoCs. The pre-integrated CSI-2 and DSI solution ensures the interoperability and makes this PHY easy to integrate, shortening the product's time to market.

Key Features

Multiple Configurations Possible. TX-only (with integrated PLL), RX-only, and combined TX and RX configurations
Complete Function for HS TX/RX, LP TX/RX, and LPCD with automatic termination control for high-speed and low-power modes
Integrated BIST Capable of producing and checking PRBS, CRPAT, and CJTPAT

Benefits

Available as Pre-Integrated Solution with Controller: Cadence CSI-2 and DSI supported
Scalable, Modular Design: Compact and regular footprint
Supports Advanced FinFET Processes: 16nm, 12nm, and 7nm processes supported

Block Diagram

Technical Specifications

TSMC

Silicon Proven: 7nm , 12nm , 16nm

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