1G Deep Buffering Memory Ethernet Switch IP Core

Overview

Advanced switch supporting buffering of large amounts of data in external DDR RAM

The 1G deep buffering memory Ethernet Switch is an advanced Ethernet switching IP that supports buffering large amounts of data in external RAM. The non-blocking Ethernet switch IP core enables fine-grained traffic differentiation for rich implementations of packet prioritization, enabling per port and per queue shaping on egress ports.

The 1G deep buffering memory Ethernet switch IP from Comcores supports MAC learning, VLAN 802.1Q, multicast and broadcast as well as IEEE 1588 transparency. Each port provides a native interface for GMII Ethernet PHY devices.

Key Features

Delivers Performance
- QoS features such as classification, queuing and priorities included
- Automatic MAC address learning and aging
- Supports buffering of up to 128 MB in DDR
- Extensive statistic reporting
Easy to use
- Solid Verification Environment
- Very easy integration on Xilinx evaluation platforms
- GMII interfaces for attaching external Physical Layer devices (PHY)
Highly Configurable
- Buffer size fully configurable
- Configurable scheduling (round-robin, strict priority, etc.)
- Configurable tagging
Silicon Agnostic
- Designed in Verilog and targeting both ASICs and FPGAs

Block Diagram

Deliverables

Code: VHDL (Source code or Encrypted RTL)
Documentation: Including User Manual and Release Note
Simulation Environment: Simple Test Environment, Test Cases and Test Scripts
Access to Support System
Synopsys Lint Waivers

Technical Specifications

TSMC

Pre-Silicon: 7nm

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