Comcores 1G Ethernet Packet Switch IP core is an advanced switch supporting buffering of large amounts of data in external RAM. The non-blocking Ethernet switch IP core enables fine-grained traffic differentiation for rich implementations of packet prioritization enabling per port and per queue shaping on egress ports.
The switch supports MAC learning, VLAN 802.1Q, multicast and broadcast as well as IEEE 1588 transparency. Each port provides a native interface for GMII Ethernet PHY devices.
Ethernet Packet Switch 1G
Overview
Key Features
- Delivers Performance
- QoS features such as classification, queuing and priorities included
- Automatic MAC address learning and aging
- Supports buffering of up to 128 MB in DDR
- Extensive statistic reporting
- Easy to use
- Solid Verification Environment
- Very easy integration on Xilinx evaluation platforms
- GMII interfaces for attaching external Physical Layer devices (PHY)
- Highly Configurable
- Buffer size fully configurable
- Configurable scheduling (round-robin, strict priority, etc.)
- Configurable tagging
- Silicon Agnostic
- Designed in Verilog and targeting both ASICs and FPGAs
Block Diagram
Deliverables
- The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note
- Simulation Environment, including Simple Testbed, Test case, Test Script
- Access to support system and direct support from Comcores Engineers
- Synopsys Lint and CDC
Technical Specifications
Maturity
High
Availability
Available
TSMC
Pre-Silicon:
7nm