10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC

Overview

The first IP for PCIe 3.1 with L1 sub-states support

The Cadence® 10Gbps Multi-Link and Multi-Protocol PHY IP provides a flexible PHY IP that simplifies the design process without compromising performance, power, or silicon die area. The PHY IP is a lower-active and low leakage power design crafted for mobile, wireless IoT, consumer, and automotive designs. The PHY IP is designed for multi-protocols running on single PHY macro and is compliant with USB 3.1, PCI Express® (PCIe®) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, 10G-KR* , QSGMII, and SGMII specifications. The PCS complies with the PIPE 4.2 interfaces, and provides support for the dynamic equalization features of different protocols. The PHY IP is architected to quickly and easily integrate into any SoC, and to connect seamlessly to Cadence or third-party PIPE-compliant controllers.It provides a cost-effective, versatile, and low-power solution for demanding applications. It offers SoC integrators the advanced capabilities, flexibility, and support that meet the requirements of high-performance designs. The PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and system and peripheral IP.

Key Features

  • Supports USB 3.1, PCIe 3.0/2.0/1.0, DP-TX v1.4/ eDP-TX v1.4b, SATA 3, 10G-KR and SGMII
  • Supports PCIe L1 sub-states
  • Supports SRIS and internal SSC generation
  • Supports internal and external clock sources with clock active detection
  • Multi-protocol support for simultaneous independent links
  • Automatic calibration of on-chip termination resistors
  • Flexible lane configuration from 1 to 8 lanes
  • SCAN, BIST, and serial/parallel loopback functions

Applications

  • Communications,
  • Consumer Electronics,
  • Data Processing,
  • Industrial and Medical,
  • Military/Civil Aerospace

Deliverables

  • Standard integration views: LEF abstract, timing views (.LIB), behavioral model (Verily), gate-level netlist, SDF, DRC, LVS, ANT reports, and GDSII layout and layer map
  • Synthesizable soft PCS with SDC
  • f Complete documentation including user guide, integration guide, and programmer guide
  • High Volume Manufacturing (HVM) kit
  • Testboards available upon request

Technical Specifications

Foundry, Node
TSMC 5nm, 7nm, 12nm, 16nm, 22nm
Maturity
Silicon proven
TSMC
Silicon Proven: 5nm , 7nm , 12nm , 16nm , 22nm
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Semiconductor IP