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Compare 7 Other for TSMC from 5 vendors (1 - 7)
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  • 28nm
  • 32Gbps, 31 order, Pseudo Random Bit Sequence Generator / Checker
    • This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions regardless of error sequence or frequency of occurrence.
    • Can be used as Generator, Checker or both. No inductors are used minimizing area and EM interference. Simple control interface, with low frequency asynchronous signals only.
    Block Diagram -- 32Gbps, 31 order, Pseudo Random Bit Sequence Generator / Checker
  • TSMC 28HPC+ Process Monitor
    • Supply 0.9V
    • SVT, HVT and ULVT P and N devices
    Block Diagram -- TSMC 28HPC+ Process Monitor
  • Process/Voltage/Temperature Sensor (Supply voltage 1.8V/0.9V)
    • TSMC 28nm 28HPC CMOS
    • High accuracy temperature and voltage measurements
    • Process detector for all-voltage threshold MOS transistors
    • Up to 16 remote temperature/voltage sensors
    Block Diagram -- Process/Voltage/Temperature Sensor (Supply voltage 1.8V/0.9V)
  • 32Gbps Pseudo Random Bit Sequence Generator/Checker
    • PRBS order: 7 or 15 based on formulas: X1=X6^X7; X1=X14^X15
    • Full bit rate at input and output up to 32Gbps
    • Generator, Checker and Counter functions
    • Accurate error count: no omissions or double counts
    • Full rate CMOS differential input data, centered with half-rate CMOS differential clock
    • Full rate CMOS differential output data, aligned with half-rate CMOS differential clock
    • Asynchronous low frequency CMOS control interface
    • Supply voltage: 0.9V
    Block Diagram -- 32Gbps Pseudo Random Bit Sequence Generator/Checker
  • 32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator/Checker
    • PRBS order: 7, 15 or 31 based on formulas: X1=X6^X7; X1=X14^X15; X1=X28^X31
    • Full bit rate at input and output up to 32Gbps
    • Generator, Checker and Counter functions
    • Accurate error count: no omissions or double counts
    • Full rate CMOS differential input data, centered with half-rate CMOS differential clock
    • Full rate CMOS differential output data, aligned with half-rate CMOS differential clock
    Block Diagram -- 32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator/Checker
  • Run Time Phase Alignment Circuit
    • 1. Sync Clock Generation in one clock duation.
    • 2. Generatted clock is Phase Aligned with the incoming data. Data can be received.
    • 3. Tx and Rx Clock can be up to +/-5% off of the frequency range. This block can accomode and can generate same tx freq at the rx side.
    • 4. This Rx Clock can be used to -
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Semiconductor IP