General Purpose PLL IP for TSMC
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General Purpose PLL IP
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General Purpose PLL IP
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- 7nm
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4.8GHz low jitter fractional-N, Digital PLL, TSMC N7, 0.75V, N/S orientation
- Pure core voltage design
- Compact IP size (< 0.013mm²) and low power consumption (1.1mW @ 3GHz)
- Compatible with commonly used crystal oscillator frequencies
- Good power noise immunity for period jitter (< ±15%/V)
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14GHz Integer-N High-Speed PLL
- Type II hybrid Integer-N LC-PLL
- Quadrature clocks at 14GHz and 7GHz
- Fast locking
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Wide Range Programmable Integer PLL on TSMC CLN7FF
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
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Wide Range Multi-Output PLL on TSMC CLN7FF
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Input and Output Frequency (including multiple outputs) for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
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PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN7FF
- High performance design emphasis for meeting low jitter requirements in PCIe Gen4 & Gen5 applications
- Implemented with Analog Bits’ proprietary LC architecture
- Low power consumption
- Spread Spectrum Clock Generation (SSCG) and tracking capability
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Low Jitter PLL on TSMC CLN7FF
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
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High Performance 20GHz PLL on TSMC CLN7FF
- Electrically Programmable PLL for multiple applications
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
- Integrated LDO to reduce deterministic jitter
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High Performance 20GHz C2C PLL on TSMC CLN7FF
- Electrically Programmable PLL for multiple applications
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
- Integrated LDO to reduce deterministic jitter
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Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
- Process portable
- Proven (65nm to 3nm)
- Full SCAN testable
- Core voltage supply
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TSMC CLN7FFLVT 7nm Ultra PLL - 15MHz-3000MHz
- New state-of-the-art architecture using high-speed digital and analog circuits that offers unprecedented operating ranges and extremely high performance.
- Ultra low jitter performance for the most demanding SerDes and ADC reference clocks.
- Ultra wide frequency range with multiplication factors over 250,000 to support 32KHz to 1GHz references.
- Precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution.