Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions

Overview

The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality clock synthesis IP that is part of the Movellus Aeonic™ platform. Designed for high reliability and fully SCAN enabled, the CGM provides extensive visibility and controllability of key clocking metrics.

The CGM is constructed using Movellus’ patented TrueDigital™ technology. The product is delivered as soft IP and implemented using the customer’s standard cell library. With proven process portability (65 nm to 3 nm) and minimal area footprint, the CGM is ideally suited for large scale distribution within an SoC.

Key Features

Process portable
Proven (65nm to 3nm)
Full SCAN testable
Core voltage supply
Low power
Detailed debug hooks
Multi-instance
Ultra-low voltage
Fine grain frequency control as low as 1 kHz steps

Benefits

Customer Configurable
Trade-off power vs. jitter for your application's needs
Wide Voltage & Frequency Range
Operating from near-threshold up to 1.6V
Up to 8X Smaller Area
Synthesizable implementation shrinks area proportionally with descending process nodes

Applications

AI processors
CPU
GPU
Vision processing
Crypto mining
Memory pooling
Satellite
Edge AI
Aerospace
Automotive

Deliverables

Soft IP

Technical Specifications

Foundry, Node

All foundries

Availability

Now

GLOBALFOUNDRIES

In Production: 12nm , 22nm , 22nm FDX , 28nm
Pre-Silicon: 12nm , 14nm , 14nm LPE , 14nm LPP , 20nm LPM , 22nm , 22nm FDX , 28nm , 28nm FDSOI , 28nm HPP , 28nm LPH , 28nm SLP
Silicon Proven: 12nm

SMIC

Pre-Silicon: 14nm

Samsung

Pre-Silicon: 4nm , 5nm , 7nm , 8nm , 10nm , 14nm

TSMC

In Production: 7nm , 12nm , 16nm , 28nm
Pre-Silicon: 3nm , 4nm , 5nm , 6nm , 7nm , 10nm , 12nm , 16nm , 20nm , 22nm , 28nm , 28nm HP , 28nm HPC , 28nm HPCP , 28nm HPL , 28nm HPM , 28nm LP

UMC