IP Catalog > Analog IP > PLL IP > Clock Generator PLL IP > Differential Clock Receiver to CML on TSMC CLN3P-CLN3X

Differential Clock Receiver to CML on TSMC CLN3P-CLN3X

Overview

The Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications requiring CML signal levels on-chip. The Receiver is designed for digital logic processes and use robust design techniques to work in noisy SoC environments, ranging from high speed communication to low power consumer applications.

The Receiver macro is implemented in Analog Bits’ proprietary architecture that uses core and IO devices operated at core voltage. In order to minimize noise coupling and maximize ease of use, the Receiver incorporates proprietary ESD structures, which is proven in several generations of processes.

Key Features

  • Differential clock receiver
  • CML differential output to chip core
  • Wide Ranges of input frequencies for diverse clocking needs
  • Implemented with Analog Bits’ proprietary architecture
  • Low power consumption
  • Programmable termination
  • Built-in hysteresis
  • Spread Spectrum tracking capability
  • Requires no additional on-chip components or band-gaps, minimizing power consumption

Technical Specifications

Foundry, Node
TSMC CLN3P-CLN3X
TSMC
Pre-Silicon: 3nm
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