Receiver/Transmitter IP for SMIC
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Receiver/Transmitter IP
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Camera 6/7-mode Combo Receiver - 1G/1.5Gbps
- The CL12684KM4-8-12-16R3AM6-7ZIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
- The CL12684KM4-8-12-16R3AM6-7ZIP is designed to support data rate in excess of maximum 1Gbps utilizing sub-LVDS / mini-LVDS / LVDS / HiSPi(SLVS-400, HiVCM) / MIPI-DPHY / CMOS-1.8V / CMOS-3.3V interface specification.
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Dual FPD-link, 30-Bits Color LVDS Receiver, 170Mhz (SVGA/FHD@120Hz) LVDS de-serializer 10:70 channel decompression with automatic de-skew
- Layout structure based on 0.13um Logic 1P6M, 1P7M, or 1P8M Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3- 1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)
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Dual RSDS Transmitter, 30-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display
- • 20 to 150 Mhz Pixel rate per channel ( 40 to 300 Mb/s SDR input, 40 to 300 Mb/s DDR output )
- • 30 DATA + 9 RSDS CLK channels
- • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
- • 1P6M layout structure based on 0.18um 1P6M generic logic process.
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Dual RSDS Transmitter, 24/18-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display
- • 20 to 150Mhz Pixel rate ( 40 to 300 Mb/s SDR input, 40 to 300 Mb/s DDR output)
- • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
- • 1P6M layout structure based on 0.18um 1P6M generic logic process.
- • 3.3V/1.8V 10% supply voltage, -40/+125C
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LVDS Transmitter 1250Mb/s, 800Mhz clock with RSDS support
- • 1P6M layout structure based on 0.18um 1P6M 1.8V
- generic logic process.
- • 3.3V/1.8V ±10% supply voltage, -40/+125°C temperature.
- • IEEE Standard 1596.3-1996 and ANSI/TIA/EIA- 644-A Specifications.
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Dual RSDS Transmitter, 30-bit color, 80-400Mb/s (SVGA/Full HDTV@120Hz)
- • 40 to 200 Mhz Pixel rate per channel ( 80 to 400 Mb/s SDR input, 80 to 400 Mb/s DDR output)
- • 30 DATA + 9 RSDS CLK channels
- • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
- • 1P6M layout structure based on 0.13um 1P6M generic logic process.