Receiver/Transmitter IP for SMIC
Welcome to the ultimate Receiver/Transmitter IP for SMIC hub! Explore our vast directory of Receiver/Transmitter IP for SMIC
All offers in
Receiver/Transmitter IP
for SMIC
Filter
Compare
10
Receiver/Transmitter IP
for SMIC
from 3 vendors
(1
-
10)
-
LVDS TX+ (Transmitter) in UMC 40LP
- Compatible with TIA/EIA-644 LVDS Standard
- 49 Mbps - 770 Mbps bandwidth/channel
- Up to 3.08 Gbps data throughput
-
1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Full Low power CMOS design
-
1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Low power CMOS design
-
2.5 Gbps Transceiver core
- 1.6 to 2.5 Gbps operation
- 1.8V power supply, CMOS design
- Low power dissipation
- Minimal external components
-
Camera sub-LVDS/mini-LVDS/LVDS/HiSPi(SLVS-400, HiVCM)/MIPI-DPHY/CMOS 6-7mode Combo-Receiver 1.5Gbps
- MIPI DPHY v1-1/MIPI CSI/TIA/EIA-644 LVDS/SLVS-400 compliant
-
Dual FPD-link, 30-Bits Color LVDS Receiver, 170Mhz (SVGA/FHD@120Hz) LVDS de-serializer 10:70 channel decompression with automatic de-skew
- Layout structure based on 0.13um Logic 1P6M, 1P7M, or 1P8M Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3- 1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)
-
Dual RSDS Transmitter, 30-bit color, 80-400Mb/s (SVGA/Full HDTV@120Hz)
- • 40 to 200 Mhz Pixel rate per channel ( 80 to 400 Mb/s SDR input, 80 to 400 Mb/s DDR output)
- • 30 DATA + 9 RSDS CLK channels
- • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
- • 1P6M layout structure based on 0.13um 1P6M generic logic process.
-
Dual RSDS Transmitter, 30-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display
- • 20 to 150 Mhz Pixel rate per channel ( 40 to 300 Mb/s SDR input, 40 to 300 Mb/s DDR output )
- • 30 DATA + 9 RSDS CLK channels
- • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
- • 1P6M layout structure based on 0.18um 1P6M generic logic process.
-
Dual RSDS Transmitter, 24/18-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display
- • 20 to 150Mhz Pixel rate ( 40 to 300 Mb/s SDR input, 40 to 300 Mb/s DDR output)
- • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
- • 1P6M layout structure based on 0.18um 1P6M generic logic process.
- • 3.3V/1.8V 10% supply voltage, -40/+125C
-
LVDS Transmitter 1250Mb/s, 800Mhz clock with RSDS support
- • 1P6M layout structure based on 0.18um 1P6M 1.8V
- generic logic process.
- • 3.3V/1.8V ±10% supply voltage, -40/+125°C temperature.
- • IEEE Standard 1596.3-1996 and ANSI/TIA/EIA- 644-A Specifications.