I/O Library IP for SMIC

Compare 199 I/O Library IP for SMIC from 16 vendors (1 - 10)

Bi-Directional LVDS with LVCMOS
- Compliant with TIA/EIA-644 LVDS standard, also meets sub-LVDS
- Receiver compatible with HSCL levels for differential clock/data input
- LVDS transmitter and receiver have independent power control
- LVDS transmitter has adjustable output current level
800MHz LVDS Cell Set for 180nm
- 400MHz (800Mb DDR) operation.
- Receive, Transmit and bias cells.
V-by-One Tx IP, Silicon Proven in SMIC 40LL
- 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
- DC coupling mode
- Multi-channel shared offset
- Built-in transmitter terminal impedance, no need for off-chip components
RF Transceiver SMIC 55nm
- 3GPP R14 NB_IOT??
- SMIC55nm??
- 2V ~ 3.6V????
- ???:??10mA,??68mA@14dBm output,200mA@22dBm output,????<1uA
LVDS TX+ (Transmitter) in UMC 40LP
- Compatible with TIA/EIA-644 LVDS Standard
- 49 Mbps - 770 Mbps bandwidth/channel
- Up to 3.08 Gbps data throughput
LVDS Receiver
- Wide frequency range:
- Power-Down Mode
- Supports VGA, SVGA, XGA, SXGA, SXGA+ and QXGA
- Up to 10.5 Gbit/s bandwidth
LVDS Transmitter
- Wide frequency range:
- Power-Down Mode
- Supports VGA, SVGA, XGA, SXGA, SXGA+ and QXGA
- On-chip Input Jitter Filtering
1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Full Low power CMOS design
1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Low power CMOS design
666 Mbps LVDS Transceiver IP
- 666 Mbps operation per channel
- Low power dissipation
- No external components
- Integrated termination resistors in transmitter and receiver.