Embedded Memories IP for SMIC

Compare 93 Embedded Memories IP for SMIC from 7 vendors (1 - 10)

1Kbyte EEPROM IP with configuration 64p8w16bit
- The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1Kbyte (16(bit per word) x 8(words per page) x 64(pages)) with single-bit output data and parallel write data in one word.
- Write EEPROM page data comes to input di<15:0> and write process execute if signal wr=“1”.
1024-bit EEPROM IP with configuration 32p2w16bit
- The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1024 bits (16(bit per word) x 2(word per page) x 32(page)), which is organized as 32 pages of 2 words by 16 bit with single-bit output data and parallel write data.
- Data writing in EEPROM consists of 2 phases - erasing and writing.
512-bit EEPROM IP with configuration 16p2w16bit
- The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 512 bits (16(bit per word) x 2(word per page) x 16(page)), which is organized as 16 pages of 2 words by 16 bit with single-bit output data and parallel write data.
- Write EEPROM page data comes to input D0<15:0> and write by words to latch through the signal SAMPLE, while the signal write in a state of «1». The address of a word written down in latches is defined by two low bits of the bus adr_bl<1:0>.
1Kbyte Embedded EEPROM with configuration 64p8w16bit
- SMIC EEPROM CMOS 0.18 um
- 1Kbyte of available memory 16(bit per word) x 8(words per page) x 64(pages) bit
Embedded flash IP, 1.5V/5V SMIC 90nmBCD
- Supports high temperature and long retention life time for severe automotive requirement
- Low power in Program/Erase operation for power critical applications
- Requires few (2~3) additional masks
- No change to SPICE model of Standard CMOS process, for re-using existing design and IP
Embedded flash IP, 1.32V/3V PSMC 90nm
- Supports high temperature and long retention life time for severe automotive requirement
- Low power in Program/Erase operation for power critical applications
- Requires few (2~3) additional masks
- No change to SPICE model of Standard CMOS process, for re-using existing design and IP
1Kbyte EEPROM with configuration 64p8w16bit
- SMIC EEPROM CMOS 0.18 um
- High density of memory cells
- Writing and erasing data by one high-voltage pulse
- Programming and erase time – 2 ms (determined by specification of the EEPROM SMIC cell)
512-bit EEPROM with configuration 16p1w32bit
- SMIC EEPROM CMOS 0.18 um
- High density of memory cells
- Writing and erasing data by one high-voltage pulse
Memory Compiler in TSMC (16nm,22nm,28nm,40nm,55nm,90BCD+,110nm,152nm,180BCD)
- Synchronous read/write operation
- Low leakage current and lower operation power consumption
- Minimum metal layer requirement: 4/3 metal layers
- High density layout structure and small area design
CSMC 0.13um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down