Dual Port SRAM Compiler IP, Support Repair Features, UMC 65nm SP process
Overview
UMC 65nm SP/RVT Logic and HVT Low-K process synchronous, high density, Dual Port SRAM compiler with the row redundancy option.
Technical Specifications
Foundry, Node
UMC 65nm SP
UMC
Pre-Silicon:
65nm
SP
Related IPs
- Single Port SRAM Compiler IP, UMC 65nm SP process
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k
- Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits
- Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process