Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits

Overview

Key Features

• Source biasing implementation for low leakage
• 4 times less leakage compared to stand by mode
• 3 times less leakage compared to retention mode
• Designed with the latest uLL PRBC from TSMC and a mix of HVT and SVT MOS (dominated by SVT to reach high speed)
• Low dynamic power
• Low voltage capability: 30% power consumption savings when operating at 1.0 V +/-10%
• Reduced die cost
• Up to 10% denser than standard memory compilers available at 90 nm
• Easy integration
• MUX options 8, 16 ,32
• Data range flexibility allows easy addition of bits for redundancy or ECC purposes
• Address range flexibility allows easy addition of single rows for redundancy purposes
• Write Mask
• Complete mismatch validation of the memory architecture taking in account local and global dispersion
• Partitioned array for best low voltage performances
• Sense amplifier optimized for low voltage operation
• High robustness thanks to self-timing access scheme
• Optional BIST for industrial fabrication test of instances
• Compliance with TSMC IP 9000 qualification process

Technical Specifications