Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process
Overview
UMC 55SP Single Port SRAM with row redundancy.
Technical Specifications
Foundry, Node
UMC 55nm SP
UMC
Pre-Silicon:
55nm
Related IPs
- Single Port SRAM Compiler IP, UMC 65nm SP process
- Single Port SRAM compiler - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits
- Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640 k