IP Catalog > Security IP > Interface Security IP

Interface Security IP

All offers in Interface Security IP
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (82)
Compare 82 Interface Security IP from 20 vendors (1 - 10)
  • 1-port Receiver/Transmitter HDCP 2.3 on DisplayPort 1.4/2.0 ESM (generation 3)
    • The HDCP 2.3 Embedded Security Modules (ESMs) on DisplayPort are autonomous modules that provide designers with a complete and robust transmitter (TX) or receiver (RX) implementation of the HDCP 2.3 content-protection technology over DisplayPort wired connections, including USB Type-C/USB 3.1.
    • This solution helps designers shorten development cycles and fully meet the stringent compliance and robustness requirements of the DCP LLC licensing authority.
    Block Diagram -- 1-port Receiver/Transmitter HDCP 2.3 on DisplayPort 1.4/2.0 ESM (generation 3)
  • HDCP Encryption-Decryption Engine
    • Real-time encryption/decryption
    • 8k compression available for select applications
    • Low gate count and low latency implementation
    • Supports HDCP 1.3 and 1.4
    Block Diagram -- HDCP Encryption-Decryption Engine
  • IPsec ESP IP core for FPGA
    • Built on the success of Helion's industry proven cryptographic IP cores, the Helion ESP Engine provides hardware acceleration of the key cryptographic algorithms and packet processing required by the IPsec Encapsulating Security Payload (ESP) protocol.
    • Its modular architecture provides the flexibility to support only those cryptographic algorithms required for a particular application to provide the optimum logic area and performance trade-off.
    Block Diagram -- IPsec ESP IP core for FPGA
  • MACsec Intel® FPGA IP
    • The MACsec Intel® FPGA IP core implements the IEEE Media Access Control Security standard as defined in 802.1AE (2018) as fully configurable soft IP
    • MACsec provides data confidentiality and integrity for the Ethernet protocol and is commonly used to secure network traffic in 5G systems, between the cloud and data center, and between IoT devices.
    Block Diagram -- MACsec Intel® FPGA IP
  • Message filter
    • Message filters are placed in the middle of a TCP / TLS session to scan application data, and discard unwanted messages and security-issue packets, reducing unnecessary traffic without increasing CPU load or latency.
    • Unlike filters by IP address or port, which scan the data content and discard or pass through packets, DPI (Deep Packet Inspection) and other methods tend to cause CPU processing load and packet processing delays.
    Block Diagram -- Message filter
  • SSL/TLS Offload Engine
    • Our SSL/TLS engine accelerates and offloads processing for encryption / decryption and authentication in SSL / TLS by combining our TCP offload and crypt engine.
    •  
    • Since the record layer processing is completely hardware offloaded, the user application can overwhelmingly reduce the CPU load which only needs preparing the data to transfer securely.
    Block Diagram -- SSL/TLS Offload Engine
  • MacSec Verification IP
    • Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)
    • Provides MacSec as per IEEE standard 802.1AE-2018 specification
      • Supports controlled and uncontrolled ports
      • Encodes and decodes MacSeC PDUs
      • Protects and validates macSec Pdus using AES-GCM-128 Cipher suites
      • Cryptographic protection
      • Modification and Addition of MSDU
      • Uses configurable secure association key for encryption and authentication
      • Supports Vlan and jumbo frames
      • Supports Replay protection and ICV Works in tandem with gPTP (IEEE 802.1AS)/ PTP (IEEE 1588)
    • Supports controlled and uncontrolled ports
    • Encodes and decodes MacSeC PDUs
    Block Diagram -- MacSec Verification IP
  • TLS Handshake Hardware Accelerator
    • RSA, ECC and more
    • > 1 GHz in 16nm
    • 400-500 MHz on mid-range/high-end FPGA
    Block Diagram -- TLS Handshake Hardware Accelerator
  • DDR Encrypter
    • Protect the external memory
    • On-the-fly encryption
    • Optional authentication
    Block Diagram -- DDR Encrypter
  • Memory & Bus Protection IP Core
    • The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory.
    • It supports AHB/AXI slave/master interfaces, APB port for configuration purpose, and contains a cache. It is typically placed between the processor(s) and an external memory controller (DDRx).
    Block Diagram -- Memory & Bus Protection IP Core
×
Semiconductor IP