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Interface Security IP

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Compare 81 Interface Security IP from 20 vendors (1 - 10)
  • Inline Decrypter & Authenticator IP Core for Automotive
    • The Inline Decrypter and Authenticator IP core enables on-the-fly execution of encrypted and signed code from Flash.
    • It is used to authenticate and decrypt code located in Flash. In addition it is ISO26262 certified (ASIL-D).
    Block Diagram -- Inline Decrypter & Authenticator IP Core for Automotive
  • Memory & Bus Protection IP Core
    • The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory.
    • It supports AHB/AXI slave/master interfaces, APB port for configuration purpose, and contains a cache.
    Block Diagram -- Memory & Bus Protection IP Core
  • Inline Decrypter IP Core
    • The Inline Decrypter IP Core enables on-the-fly execution of encrypted code from Flash.
    • It is often used to protect the source code from decompiling or reverse engineering.
    Block Diagram -- Inline Decrypter IP Core
  • DDR Encrypter
    • Protect the external memory
    • On-the-fly encryption
    • Optional authentication
    Block Diagram -- DDR Encrypter
  • IPsec Engine

    • The IPsec Engine implements RFC4301 and other relevant RFCs, providing confidentiality, connectionless data integrity, data-origin authentication and replay protection on OSI layer 3.

    Block Diagram -- IPsec Engine
  • 1.6 Tbps MACsec Engine
    • Throughput up to 1.5Tb
    • ASIC and FPGA
    • Multi-channel support for link aggregation or FlexE
    Block Diagram -- 1.6 Tbps MACsec Engine
  • Network Security Crypto Accelerator
    • The Network Security Crypto Accelerator is a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
    • This IP is used to accelerate/offload MACsec, IPsec, VPN, TLS/SSL, disk encryption, or any other custom application, requiring symmetric cryptography algorithms.
    Block Diagram -- Network Security Crypto Accelerator
  • Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
    • One input word per clock without any backpressure
    • Design can switch stream, algorithm, mode, key and/or direction every clock cycle
    • GCM: throughput is solely determined by the data width, data alignment and clock frequency
    • XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
    Block Diagram -- Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
  • 1.6T/3.2T Multi-Channel MACsec Engine with TDM Interface (MACsec-IP-364)
    • The MACsec-IP-364 is a MACsec/IPsec engine developed specifically for high-speed, multi-rate and multi-port Ethernet devices.
    • Its architecture provides an optimal multi-protocol solution for aggregate throughput for 1.6T and 3.2T.
    • The MACsec-IP-364 is ideal for deployment in data center, enterprise and carrier network applications, as well as network-attached high-performance computing.
    Block Diagram -- 1.6T/3.2T Multi-Channel MACsec Engine with TDM Interface (MACsec-IP-364)
  • Ethernet Switch/Router Datacenter ToR 32x100G
    •  32 x 100 Gigabit Ethernet ports.
    •  Full wire-speed on all ports and all Ethernet frame sizes.
    •  Store and forward shared memory architecture.
    •  Support for jumbo packets up to 32738 bytes.
    Block Diagram -- Ethernet Switch/Router Datacenter ToR 32x100G
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