Dual-Port SRAM IP

Compare 143 Dual-Port SRAM IP from 13 vendors (1 - 10)

MRAM Synthesizable Transactor
- Supports all the MRAM commands as per the MR2A16A and MR0A08B specifications.
- Supports Symmetrical high-speed read and write with fast access time.
- Supports SRAM Compatible timing
- Supports native non-volatility
CodaCache® Last Level Cache IP
- Standalone IP
- 1.2 GHz frequency in 16FF+TT process
- Protocol interoperability: AMBA AXI 4
Memory Compiler
- 70-90% power reduction
- Unmatched performance
- Multi-technology support
- Tailored for design needs
Memory Compiler
- High-Density Memory Compilers
- Ultra-High-Speed Memory Compilers
- Low-Power Memory Compilers
GF 0.13um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
CSMC 0.18um 90% shrunk Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
CSMC 0.13umLP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
- Low Leakage
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
CSMC 0.13um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
Low power, high speed, and high density configurable SRAM
- Based on foundry provided 6T SRAM cell
- Reliable, silicon proven architecture
- Best-in-class active power, leakage current, density, and speed
- Supports large instances (e.g. 16Mbit)
Low power, high speed, and high density configurable Double Density SRAM
- Based on patent-pending 1T cell design
- Implemented with unmodified standard CMOS logic process
- Best-in-class active power, leakage current, density, and speed
- Supports large instances (e.g. 32Mbit)