Power-On-Reset IP

Overview

The Power-On-Reset (POR) IP provides reliable reset functions for general applications. It is powered by analog supply and monitors both analog and digital supply.

The POR IP generates a POR signal to reset the digital logic. The POR signal is set low if analog supply or digital supply falls below the threshold voltage, and will be set high if both of analog supply and digital supply exceed the threshold voltage.

Key Features

Low power consumption
Built-in low-power bandgap reference
Supports multiple voltage levels for versatile applications
Ensures quick and reliable system initialization
Robust against power supply fluctuations and glitches
Reliable operation across a wide temperature range

Benefits

Low power consumption
Fully customizable
Small area
Simple integration process
Chip level integration

Block Diagram

Applications

Microcontrollers & Microprocessors
Integrated Circuits
Automotive Electronics
Industrial Control Systems

Deliverables

Datasheet
Physical Integration Guide
Timing Library Model (LIB)
Encrypted Verilog Model
Library Exchange Format (LEF)
GDSII Database
Evaluation Board if Available

Technical Specifications

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