Why 450mm Will Be Pushed-Back Even Further
A Must-See Chart From ISSCC2014
The chart shown below was presented at ISSCC 2014 by Dinesh Maheshwari, CTO of the Memory Products Division at Cypress Semiconductors. The slide clearly illustrates that embedded SRAM ("eSRAM") scaling is broken.
Instead of the expected 4X density improvement for a large memory block with two nodes of scaling, the improvement range is only 1.6X for low performance to 1.1X at good performance. Since eSRAM dominates most SoC silicon area, we have to conclude that dimensional scaling is broken as well. Let's discuss this further…
To read the full article, click here
Related Semiconductor IP
- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- Simulation VIP for AMBA CHI-C2C
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
Related Blogs
- Why IC Prices Will Be High In 2011
- Global semiconductor market will be $313 billion in 2012: SSIA
- Global semiconductor industry keeps consolidating; 28nm will be stable: Dr. Wally Rhines
- Will your next ASIC ever be an FPGA?
Latest Blogs
- A Comparison on Different AMBA 5 CHI Verification IPs
- Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum
- Accelerating Development Cycles and Scalable, High-Performance On-Device AI with New Arm Lumex CSS Platform
- Desktop-Quality Ray-Traced Gaming and Intelligent AI Performance on Mobile with New Arm Mali G1-Ultra GPU
- Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet