Why 450mm Will Be Pushed-Back Even Further
March 3, 2014
A Must-See Chart From ISSCC2014
The chart shown below was presented at ISSCC 2014 by Dinesh Maheshwari, CTO of the Memory Products Division at Cypress Semiconductors. The slide clearly illustrates that embedded SRAM ("eSRAM") scaling is broken.
Instead of the expected 4X density improvement for a large memory block with two nodes of scaling, the improvement range is only 1.6X for low performance to 1.1X at good performance. Since eSRAM dominates most SoC silicon area, we have to conclude that dimensional scaling is broken as well. Let's discuss this further…
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related Blogs
- Why IC Prices Will Be High In 2011
- Global semiconductor market will be $313 billion in 2012: SSIA
- Global semiconductor industry keeps consolidating; 28nm will be stable: Dr. Wally Rhines
- Will your next ASIC ever be an FPGA?
Latest Blogs
- Evolution of CXL PBR Switch in the CXL Fabric
- CNNs and Transformers: Decoding the Titans of AI
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success