Why 450mm Will Be Pushed-Back Even Further
March 3, 2014
A Must-See Chart From ISSCC2014
The chart shown below was presented at ISSCC 2014 by Dinesh Maheshwari, CTO of the Memory Products Division at Cypress Semiconductors. The slide clearly illustrates that embedded SRAM ("eSRAM") scaling is broken.
Instead of the expected 4X density improvement for a large memory block with two nodes of scaling, the improvement range is only 1.6X for low performance to 1.1X at good performance. Since eSRAM dominates most SoC silicon area, we have to conclude that dimensional scaling is broken as well. Let's discuss this further…
To read the full article, click here
Related Semiconductor IP
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
Related Blogs
- Need really big FPGAs? Xilinx will be taking the "3D" route for initial Virtex 7 parts
- Why IC Prices Will Be High In 2011
- Global semiconductor market will be $313 billion in 2012: SSIA
- Global semiconductor industry keeps consolidating; 28nm will be stable: Dr. Wally Rhines
Latest Blogs
- Cadence Leads the Way at PCI-SIG DevCon 2025 with Groundbreaking PCIe 7.0 Demos
- Introducing the Akeana 1000 Series Processors
- How fast a GPU do you need for your user interface?
- PCIe 6.x and 112 Gbps Ethernet: Synopsys and TeraSignal Achieve Optical Interconnect Breakthroughs
- Powering the Future of RF: Falcomm and GlobalFoundries at IMS 2025