VIP Architecture: Why Native SystemVerilog and UVM?
January 14, 2015
Four years ago, we talked to several key customers, and decisively moved all our VIP development to an architecture based on SystemVerilog and UVM. In this short video, you can learn about the benefits of using such VIP for verifying your SoCs: ease-of-use, productivity and accelerated coverage closure.
Related Semiconductor IP
- Camera Interface (AHB Bus)
- ITU-R BT.1120 Decoder – HD 1920x1080p
- ITU-R BT.656 Decoder
- ITU-R BT.656 Encoder
- Color Space converter & Chroma Resampler- 4:4:4 RGB to 4:2:2 Y’CbCr
Related Blogs
- SystemVerilog Protocol Compliance: Why Source-code Test Suites?
- Virtual Sequences in UVM: Why, How?
- Why AI Requires a New Chip Architecture
- VIP Portfolio Expands for Data-Intensive Hyperscale Data Centers, HPC, and AI/ML