Unleashing the Potential of RISC-V: A Recap of the SiFive Tech Forum
As the inventors of RISC-V and performance density leaders, SiFive is committed to spreading the word about how this groundbreaking open architecture is reshaping the computing industry and ushering in new possibilities. Last week, we hosted the SiFive Tech Forum in Hsinchu, the technology heart of Taiwan, to bring together hardware engineers, developers, and other technology leaders to talk about the incredible momentum of RISC-V to-date and how SiFive is leading the RISC-V revolution. The event was well over subscribed, which highlighted the eagerness with which the attendees were keen to learn about the latest SiFive solutions. Read on to find out more about what we covered during the SiFive Tech Forum.
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Related Semiconductor IP
- RISC-V CPU IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
- RISC-V High Performance Processor
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
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