DAC 2024 - Showcasing the future of RISC-V through EDA
As I sat on the plane in Boston it’s fair to say that I was curious about what DAC 2024 would bring. The previous year was much better than I expected but a cold June in San Francisco wasn’t exactly what I was dreaming about. Afterall, while I was heading to San Francisco with a bunch of other Codasippers some of the Codasip team was headed for the RISC-V Summit in Munich.
The event is nowhere on the scale that it used to be. In fact, the entire exhibit could probably now fill one floor of the Moscone. But the level of foot traffic remained high throughout the show and the team and I spoke to a fair number of people over the 3 days of exhibits. I was impressed with the number of fresh faces and new startups. There was something interesting to see in all corners of the tradeshow floor. And… incredibly the weather was, well, incredible.
To read the full article, click here
Related Semiconductor IP
- RISC-V CPU IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
- RISC-V High Performance Processor
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
Related Blogs
- DAC retrospective
- Heard at DAC: Is workflow automation the next frontier for EDA?
- DAC 2012 Gary Smith EDA Kickoff: EDA and ESL Growth and Four Different Software Virtual Prototypes
- DAC 2014 Keynote: EDA Can Tap Into New Revenue Streams
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview