DAC 2024 - Showcasing the future of RISC-V through EDA
As I sat on the plane in Boston it’s fair to say that I was curious about what DAC 2024 would bring. The previous year was much better than I expected but a cold June in San Francisco wasn’t exactly what I was dreaming about. Afterall, while I was heading to San Francisco with a bunch of other Codasippers some of the Codasip team was headed for the RISC-V Summit in Munich.
The event is nowhere on the scale that it used to be. In fact, the entire exhibit could probably now fill one floor of the Moscone. But the level of foot traffic remained high throughout the show and the team and I spoke to a fair number of people over the 3 days of exhibits. I was impressed with the number of fresh faces and new startups. There was something interesting to see in all corners of the tradeshow floor. And… incredibly the weather was, well, incredible.
Related Semiconductor IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
- RISC-V High Performance Processor
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32 Bit - Embedded RISC-V Processor Core
Related Blogs
- Sunny skies and electric energy: RISC-V Summit Europe 2024 shines in Munich
- DAC retrospective
- Heard at DAC: Is workflow automation the next frontier for EDA?
- DAC 2012 Gary Smith EDA Kickoff: EDA and ESL Growth and Four Different Software Virtual Prototypes
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?